Logic Families
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NAND gate. The circuit shown is that of one of the four gates inside a quad two-input NAND (type
74F00 or 54F00). The DTL kind of input with emitter follower configuration of Q 1 provides a good
base drive to Q 2 . The ‘Miller killer’ configuration comprising varactor diode D 7 , transistor Q 6 and
associated components speeds up LOW-to-HIGH transition. During LOW-to-HIGH transition, voltage
at the emitter terminal of Q 3 begins to rise while Q 5 is still conducting. Varactor diode D 7 conducts,
thus supplying base current to Q 6 . A conducting Q 6 provides a discharge path for the charge stored in
the base-collector capacitance of Q 5 , thus expediting its turn-off.
5.3.9.1 Characteristic Features
Characteristic features of this family are summarized as follows: V IH = 2 V; V IL = 0.8 V; I IH = 20 A;
I IL = 0.6 mA; V OH = 2.7 V; V OL = 0.5 V; I OH = 1 mA; I OL = 20 mA; V CC = 4.75–5.25 V (74F) and 4.5–
5.5 V (54F); propagation delay (a load resistance of 500 , a load capacitance of 50 pF and full
operating voltage and temperature ranges) = 5.3 ns/7 ns (max.) for LOW-to-HIGH and 6 ns/6.5 ns
(max.) for HIGH-to-LOW output transitions (74AS/54AS); worst-case noise margin = 0.3 V; fanout = 40; I CCH (for all four gates) = 2.8 mA; I CCL (for all four gates) = 10.2 mA; operating temperature
range = 0–70 °C (74F-series) and −55 to +125 °C (54F-series); speed–power product = 10 pJ;
maximum flip-flop toggle frequency = 125 MHz.
5.3.10 Floating and Unused Inputs
The floating input of TTL family devices behaves as if logic HIGH has been applied to the input. Such
behaviour is explained from the input circuit of a TTL device. When the input is HIGH, the input
emitter-base junction is reverse biased and the current that flows into the input is the reverse-biased
diode leakage current. The input diode will be reverse biased even when the input terminal is left
unconnected or floating, which implies that a floating input behaves as if there were logic HIGH
applied to it.
As an initial thought, we may tend to believe that it should not make any difference if we leave
the unused inputs of NAND and AND gates as floating, as logic HIGH like behaviour of the floating
input makes no difference to the logical behaviour of the gate, as shown in Figs 5.24(a) and (b). In
spite of this, it is strongly recommended that the unused inputs of AND and NAND gates be connected
to a logic HIGH input [Fig. 5.24(c)] because floating input behaves as an antenna and may pick up
stray noise and interference signals, thus causing the gate to function improperly. 1 k resistance is
connected to protect the input from any current spikes caused by any spikes on the power supply line.
More than one unused input (up to 50) can share the same 1 k resistance, if needed.
In the case of OR and NOR gates, unused inputs are connected to ground (logic LOW), as shown in
Fig. 5.25(c), for obvious reasons. A floating input or an input tied to logic HIGH in this case produces
a permanent logic HIGH (for an OR gate) and LOW (for a NOR gate) at the output as shown in
Figs 5.25(a) and (b) respectively. An alternative solution is shown in Fig. 5.25(d), where the unused
input has been tied to one of the used inputs. This solution works well for all gates, but one has to be
conscious of the fact that the fan-out capability of the output driving the tied inputs is not exceeded.
If we recall the internal circuit schematics of AND and NAND gates, we will appreciate that, when
more than one input is tied together, the input loading, that is, the current drawn by the tied inputs
from the driving gate output, in the HIGH state is n times the loading of one input (Fig. 5.26); n is
the number of inputs tied together. When the output is LOW, the input loading is the same as that of
a single input. The reason for this is that, in the LOW input state, the current flowing out of the gate
is determined by the resistance R 1 , as shown in Fig. 5.27. However, the same is not true in the case of
141
NAND gate. The circuit shown is that of one of the four gates inside a quad two-input NAND (type
74F00 or 54F00). The DTL kind of input with emitter follower configuration of Q 1 provides a good
base drive to Q 2 . The ‘Miller killer’ configuration comprising varactor diode D 7 , transistor Q 6 and
associated components speeds up LOW-to-HIGH transition. During LOW-to-HIGH transition, voltage
at the emitter terminal of Q 3 begins to rise while Q 5 is still conducting. Varactor diode D 7 conducts,
thus supplying base current to Q 6 . A conducting Q 6 provides a discharge path for the charge stored in
the base-collector capacitance of Q 5 , thus expediting its turn-off.
5.3.9.1 Characteristic Features
Characteristic features of this family are summarized as follows: V IH = 2 V; V IL = 0.8 V; I IH = 20 A;
I IL = 0.6 mA; V OH = 2.7 V; V OL = 0.5 V; I OH = 1 mA; I OL = 20 mA; V CC = 4.75–5.25 V (74F) and 4.5–
5.5 V (54F); propagation delay (a load resistance of 500 , a load capacitance of 50 pF and full
operating voltage and temperature ranges) = 5.3 ns/7 ns (max.) for LOW-to-HIGH and 6 ns/6.5 ns
(max.) for HIGH-to-LOW output transitions (74AS/54AS); worst-case noise margin = 0.3 V; fanout = 40; I CCH (for all four gates) = 2.8 mA; I CCL (for all four gates) = 10.2 mA; operating temperature
range = 0–70 °C (74F-series) and −55 to +125 °C (54F-series); speed–power product = 10 pJ;
maximum flip-flop toggle frequency = 125 MHz.
5.3.10 Floating and Unused Inputs
The floating input of TTL family devices behaves as if logic HIGH has been applied to the input. Such
behaviour is explained from the input circuit of a TTL device. When the input is HIGH, the input
emitter-base junction is reverse biased and the current that flows into the input is the reverse-biased
diode leakage current. The input diode will be reverse biased even when the input terminal is left
unconnected or floating, which implies that a floating input behaves as if there were logic HIGH
applied to it.
As an initial thought, we may tend to believe that it should not make any difference if we leave
the unused inputs of NAND and AND gates as floating, as logic HIGH like behaviour of the floating
input makes no difference to the logical behaviour of the gate, as shown in Figs 5.24(a) and (b). In
spite of this, it is strongly recommended that the unused inputs of AND and NAND gates be connected
to a logic HIGH input [Fig. 5.24(c)] because floating input behaves as an antenna and may pick up
stray noise and interference signals, thus causing the gate to function improperly. 1 k resistance is
connected to protect the input from any current spikes caused by any spikes on the power supply line.
More than one unused input (up to 50) can share the same 1 k resistance, if needed.
In the case of OR and NOR gates, unused inputs are connected to ground (logic LOW), as shown in
Fig. 5.25(c), for obvious reasons. A floating input or an input tied to logic HIGH in this case produces
a permanent logic HIGH (for an OR gate) and LOW (for a NOR gate) at the output as shown in
Figs 5.25(a) and (b) respectively. An alternative solution is shown in Fig. 5.25(d), where the unused
input has been tied to one of the used inputs. This solution works well for all gates, but one has to be
conscious of the fact that the fan-out capability of the output driving the tied inputs is not exceeded.
If we recall the internal circuit schematics of AND and NAND gates, we will appreciate that, when
more than one input is tied together, the input loading, that is, the current drawn by the tied inputs
from the driving gate output, in the HIGH state is n times the loading of one input (Fig. 5.26); n is
the number of inputs tied together. When the output is LOW, the input loading is the same as that of
a single input. The reason for this is that, in the LOW input state, the current flowing out of the gate
is determined by the resistance R 1 , as shown in Fig. 5.27. However, the same is not true in the case of