Logic Families
139
V CC = 4.5–5.5 V; propagation delay (for a load resistance of 500 , a load capacitance of 50 pF,
V CC = 4.5–5.5 V and an ambient temperature of minimum to maximum) = 11 ns/16 ns (max.) for
LOW-to-HIGH and 8 ns/13 ns for HIGH-to-LOW output transitions (74ALS/54ALS); worst-case noise
margin = 0.3 V; fan-out = 20; I CCH (for all four gates) = 0.85 mA; I CCL (for all four gates) = 3 mA;
operating temperature range = 0–70 °C (74-series) and −55 to +125 °C (54-series); speed–power
product = 4.8 pJ; maximum flip-flop toggle frequency = 70 MHz.
5.3.8 Advanced Schottky TTL (74AS/54AS)
Figure 5.22 shows the internal schematic of an advanced Schottky TTL NAND gate. The circuit shown
is that of one of the four gates inside a quad two-input NAND (type 74AS00 or 54AS00). Salient
R 1
10K
R 2
2K
R 6
26
V CC
Q 7
R 3
2K
Q 6
Q 2
Q 1A
D 2A
D 1A
Input A
Q 3
R 4
1K
R 5
2K
Q 5
Q 4
D 2B
D 1B
Input B
Q 1B
D 3
R 9
30K
D 5
Q 9
R 8
1K
D 4
R 7
50K
D 6
D 7
R 11
100
Q 10
R 10
25K
Q 8
D 9
Output
D 8
Figure 5.22 NAND gate in the AS-TTL.