138
Digital Electronics
R 1
37K
R 2
50K
R 3
14K
R 7
50
V CC
Q 7
R 4
5K
Q 6
Q 2
D 3
Q 1A
D 2A
D 1A
Input A
Q 3
R 5
2.8K
R 6
5.6K
Q 5
Q 4
D 2B
D 1B
Input B
Q 1B
D 4
Output
Figure 5.21 NAND gate in the ALS-TTL.
Figure 5.21 shows the internal schematic of an advanced low-power Schottky TTL NAND gate. The
circuit shown is that of one of the four gates inside a quad two-input NAND (type 74ALS00 or
54ALS00) The multi-emitter input transistor is replaced by two PNP transistors Q 1A and Q 1B . Diodes
D 1A and D 1B provide input clamping to negative excursions. Buffering offered by Q 1A or Q 1B and Q 2
reduces the LOW-level input current by a factor of (1 + h FE of Q 1A . HIGH-level output voltage is
determined primarily by V CC , transistors Q 6 and Q 7 and resistors R 4 and R 7 and is typically (V CC − 2)
V. LOW-level output voltage is determined by the turn-on characteristics of Q 5 . Transistor Q 5 gets
sufficient base drive through R 3 and a conducting Q 3 whose base terminal in turn is driven by a
conducting Q 2 whenever either or both inputs are HIGH. Transistor Q 4 provides active turn-off for Q 5 .
5.3.7.1 Characteristic Features
Characteristic features of this family are summarized as follows: V IH = 2 V; V IL = 0.8 V; I IH = 20 A;
I IL = 0.1 mA; V OH = (V CC − 2) V; V OL = 0.5 V; I OH = 0.4 mA; I OL = 8 mA (74ALS) and 4 mA (54ALS);