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Digital Electronics
• Enable time from the LOW state, t pZL . Defined for a tristate device, this is the time delay between
specified voltage points on the input and output waveforms with the tristate output changing from
the high-impedance state to the logic LOW level.
• Maximum clock frequency, f max . This is the maximum frequency at which the clock input of a
flip-flop can be driven through its required sequence while maintaining stable transitions of logic
level at the output in accordance with the input conditions and the product specification. It is also
referred to as the maximum toggle rate for a flip-flop or counter device.
• Power dissipation. The power dissipation parameter for a logic family is specified in terms of
power consumption per gate and is the product of supply voltage V CC and supply current I CC . The
supply current is taken as the average of the HIGH-level supply current I CCH and the LOW-level
supply current I CCL .
• Speed–power product. The speed of a logic circuit can be increased, that is, the propagation delay
can be reduced, at the expense of power dissipation. We will recall that, when a bipolar transistor
switches between cut-off and saturation, it dissipates the least power but has a large associated
switching time delay. On the other hand, when the transistor is operated in the active region, power
dissipation goes up while the switching time decreases drastically. It is always desirable to have in
a logic family low values for both propagation delay and power dissipation parameters. A useful
figure-of-merit used to evaluate different logic families is the speed–power product, expressed in
picojoules, which is the product of the propagation delay (measured in nanoseconds) and the power
dissipation per gate (measured in milliwatts).
• Fan-out. The fan-out is the number of inputs of a logic function that can be driven from a single
output without causing any false output. It is a characteristic of the logic family to which the device
belongs. It can be computed from I OH /I IH in the logic HIGH state and from I OL /I IL in the logic LOW
state. If, in a certain case, the two values I OH /I IH and I OL /I IL are different, the fan-out is taken as the
smaller of the two. This description of the fan-out is true for bipolar logic families like TTL and
ECL. When determining the fan-out of CMOS logic devices, we should also take into consideration
how much input load capacitance can be driven from the output without exceeding the acceptable
value of propagation delay.
• Noise margin. This is a quantitative measure of noise immunity offered by the logic family. When
the output of a logic device feeds the input of another device of the same family, a legal HIGH
logic state at the output of the feeding device should be treated as a legal HIGH logic state by the
input of the device being fed. Similarly, a legal LOW logic state of the feeding device should be
treated as a legal LOW logic state by the device being fed. We have seen in earlier paragraphs while
defining important characteristic parameters that legal HIGH and LOW voltage levels for a given
logic family are different for outputs and inputs. Figure 5.5 shows the generalized case of legal
HIGH and LOW voltage levels for output [Fig. 5.5(a)] and input [Fig. 5.5(b)]. As we can see from
the two diagrams, there is a disallowed range of output voltage levels from V OL (max.) to V OH (min.)
and an indeterminate range of input voltage levels from V IL (max.) to V IH (min.). Since V IL (max.) is
greater than V OL (max.), the LOW output state can therefore tolerate a positive voltage spike equal
to V IL (max.) − V OL (max.) and still be a legal LOW input. Similarly, V OH (min.) is greater than V IH
(min.), and the HIGH output state can tolerate a negative voltage spike equal to V OH (min.) − V IH
(min.) and still be a legal HIGH input. Here, V IL (max.) − V OL (max.) and V OH (min.) − V IH (min.)
are respectively known as the LOW-level and HIGH-level noise margin.
Let us illustrate it further with the help of data for the standard TTL family. The minimum legal
HIGH output voltage level in the case of the standard TTL is 2.4 V. Also, the minimum legal HIGH
input voltage level for this family is 2 V. This implies that, when the output of one device feeds the
input of another, there is an available margin of 0.4 V. That is, any negative voltage spikes of amplitude
Digital Electronics
• Enable time from the LOW state, t pZL . Defined for a tristate device, this is the time delay between
specified voltage points on the input and output waveforms with the tristate output changing from
the high-impedance state to the logic LOW level.
• Maximum clock frequency, f max . This is the maximum frequency at which the clock input of a
flip-flop can be driven through its required sequence while maintaining stable transitions of logic
level at the output in accordance with the input conditions and the product specification. It is also
referred to as the maximum toggle rate for a flip-flop or counter device.
• Power dissipation. The power dissipation parameter for a logic family is specified in terms of
power consumption per gate and is the product of supply voltage V CC and supply current I CC . The
supply current is taken as the average of the HIGH-level supply current I CCH and the LOW-level
supply current I CCL .
• Speed–power product. The speed of a logic circuit can be increased, that is, the propagation delay
can be reduced, at the expense of power dissipation. We will recall that, when a bipolar transistor
switches between cut-off and saturation, it dissipates the least power but has a large associated
switching time delay. On the other hand, when the transistor is operated in the active region, power
dissipation goes up while the switching time decreases drastically. It is always desirable to have in
a logic family low values for both propagation delay and power dissipation parameters. A useful
figure-of-merit used to evaluate different logic families is the speed–power product, expressed in
picojoules, which is the product of the propagation delay (measured in nanoseconds) and the power
dissipation per gate (measured in milliwatts).
• Fan-out. The fan-out is the number of inputs of a logic function that can be driven from a single
output without causing any false output. It is a characteristic of the logic family to which the device
belongs. It can be computed from I OH /I IH in the logic HIGH state and from I OL /I IL in the logic LOW
state. If, in a certain case, the two values I OH /I IH and I OL /I IL are different, the fan-out is taken as the
smaller of the two. This description of the fan-out is true for bipolar logic families like TTL and
ECL. When determining the fan-out of CMOS logic devices, we should also take into consideration
how much input load capacitance can be driven from the output without exceeding the acceptable
value of propagation delay.
• Noise margin. This is a quantitative measure of noise immunity offered by the logic family. When
the output of a logic device feeds the input of another device of the same family, a legal HIGH
logic state at the output of the feeding device should be treated as a legal HIGH logic state by the
input of the device being fed. Similarly, a legal LOW logic state of the feeding device should be
treated as a legal LOW logic state by the device being fed. We have seen in earlier paragraphs while
defining important characteristic parameters that legal HIGH and LOW voltage levels for a given
logic family are different for outputs and inputs. Figure 5.5 shows the generalized case of legal
HIGH and LOW voltage levels for output [Fig. 5.5(a)] and input [Fig. 5.5(b)]. As we can see from
the two diagrams, there is a disallowed range of output voltage levels from V OL (max.) to V OH (min.)
and an indeterminate range of input voltage levels from V IL (max.) to V IH (min.). Since V IL (max.) is
greater than V OL (max.), the LOW output state can therefore tolerate a positive voltage spike equal
to V IL (max.) − V OL (max.) and still be a legal LOW input. Similarly, V OH (min.) is greater than V IH
(min.), and the HIGH output state can tolerate a negative voltage spike equal to V OH (min.) − V IH
(min.) and still be a legal HIGH input. Here, V IL (max.) − V OL (max.) and V OH (min.) − V IH (min.)
are respectively known as the LOW-level and HIGH-level noise margin.
Let us illustrate it further with the help of data for the standard TTL family. The minimum legal
HIGH output voltage level in the case of the standard TTL is 2.4 V. Also, the minimum legal HIGH
input voltage level for this family is 2 V. This implies that, when the output of one device feeds the
input of another, there is an available margin of 0.4 V. That is, any negative voltage spikes of amplitude