Contents
xiii
9.11.3
Verilog
339
9.11.4
Java HDL
340
9.12
Application Information on PLDs
340
9.12.1
SPLDs
340
9.12.2
CPLDs
343
9.12.3
FPGAs
349
Review Questions
352
Problems
353
Further Reading
355
10 Flip-Flops and Related Devices
357
10.1
Multivibrator
357
10.1.1
Bistable Multivibrator
357
10.1.2
Schmitt Trigger
358
10.1.3
Monostable Multivibrator
360
10.1.4
Astable Multivibrator
362
10.2
Integrated Circuit (IC) Multivibrators
363
10.2.1
Digital IC-Based Monostable Multivibrator
363
10.2.2
IC Timer-Based Multivibrators
363
10.3
R-S Flip-Flop
373
10.3.1
R-S Flip-Flop with Active LOW Inputs
374
10.3.2
R-S Flip-Flop with Active HIGH Inputs
375
10.3.3
Clocked R-S Flip-Flop
377
10.4
Level-Triggered and Edge-Triggered Flip-Flops
381
10.5
J -K Flip-Flop
382
10.5.1
J -K Flip-Flop with PRESET and CLEAR Inputs
382
10.5.2
Master–Slave Flip-Flops
382
10.6
Toggle Flip-Flop (T Flip-Flop)
390
10.6.1
J-K Flip-Flop as a Toggle Flip-Flop
391
10.7
D Flip-Flop
394
10.7.1
J -K Flip-Flop as D Flip-Flop
395
10.7.2
D Latch
395
10.8
Synchronous and Asynchronous Inputs
398
10.9
Flip-Flop Timing Parameters
399
10.9.1
Set-Up and Hold Times
399
10.9.2
Propagation Delay
399
10.9.3
Clock Pulse HIGH and LOW Times
401
10.9.4
Asynchronous Input Active Pulse Width
401
10.9.5
Clock Transition Times
402
10.9.6
Maximum Clock Frequency
402
10.10 Flip-Flop Applications
402
10.10.1 Switch Debouncing
402
10.10.2 Flip-Flop Synchronization
404
10.10.3 Detecting the Sequence of Edges
404
10.11 Application-Relevant Data
407
Review Questions
408
Problems
409
Further Reading
410