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Digital Electronics
a b c
d
e f
'1'
'1'
(b)
(a)
Figure 4.21 Example 4.9.
a b c
d
e
'0’
'1'
f
Figure 4.22 Solution to example 4.9.
Example 4.10
Refer to the INHIBIT gate shown in Fig. 4.23(a) and the INHIBIT input waveform shown in Fig.
4.23(b). Sketch the output waveform.
Solution
The output will always be at logic ‘1’ level as two of the inputs of the logic gate, which is a NAND,
are permanently tied to logic ‘0’ level. This would have been so even if one of the inputs of the gate
were at logic ‘0’ level.
(a)
I/P
'1' '0'
Logic '1'
Logic '0'
1
2
3
4
5
t(ms)
(b)
Figure 4.23 Example 4.10.