Logic Gates and Related Devices
83
which is basically an AND gate with one of its inputs negated by an inverter. The negated input acts
to inhibit the gate. In other words, the gate will behave like an AND gate only when the negated input
is driven to a logic ‘0’. Figure 4.20 shows the circuit symbol and truth table of a four-input INHIBIT
gate.
Example 4.9
Refer to the INHIBIT gate of Fig. 4.21(a). If the waveform of Fig. 4.21(b) is applied to the INHIBIT
input, draw the waveform at the output.
Solution
Since all other inputs of the gate have been permanently tied to logic ‘1’ level, a logic ‘0’ at the
INHIBIT input would produce a logic ‘1’ at the output and a logic ‘1’ at the INHIBIT input would
produce a logic ‘0’ at the output. The output waveform is therefore the inversion of the input waveform
and is shown in Fig. 4.22.
A
Y
B
C
D
(a)
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
(b)
Figure 4.20 INHIBIT gate.