386
M. Mann and C. Barrett
30. Peled, D.: Verification for robust specification. In: Gunter, E.L., Felty, A. (eds.)
Theorem Proving in Higher Order Logics. pp. 231–241. Springer Berlin Heidelberg,
Berlin, Heidelberg (1997)
31. Peled, D.A., Wilke, T., Wolper, P.: An algorithmic approach for checking closure
properties of temporal logic specifications and omega-regular languages. Theor.
Comput. Sci. 195(2), 183–203 (1998)
32. Price, D.: Pentium fdiv flaw-lessons learned. IEEE Micro 15(2), 86–88 (April 1995).
https://doi.org/10.1109/40.372360
33. Sagstetter, F., Lukasiewycz, M., Steinhorst, S., Wolf, M., Bouard, A., R. Harris, W., Jha, S., Peyrin, T., Poschmann, A., Chakraborty, S.: Security challenges in automotive hardware/software architecture design. pp. 458–463 (01 2013).
https://doi.org/10.7873/DATE.2013.102
34. Shacham, O., Azizi, O., Wachs, M., Richardson, S., Horowitz, M.: Rethinking digital design: Why design must change. IEEE Micro 30(6), 9–24 (2010)
35. Strichman, O.: Tuning SAT checkers for bounded model checking. In: CAV. Lecture
Notes in Computer Science, vol. 1855, pp. 480–494. Springer (2000)
36. Strichman, O.: Accelerating bounded model checking of safety properties. Formal
Methods in System Design 24(1), 5–24 (2004)
37. Wang, C., Yang, Z., Kahlon, V., Gupta, A.: Peephole partial order reduction. In:
Ramakrishnan, C.R., Rehof, J. (eds.) Tools and Algorithms for the Construction
and Analysis of Systems. pp. 382–396. Springer Berlin Heidelberg, Berlin, Heidelberg (2008)
38. Wolf, C., Glaser, J., Kepler, J.: Yosys-a free Verilog synthesis suite. In: Proceedings
of the 21st Austrian Workshop on Microelectronics (Austrochip) (2013)
Open Access This chapter is licensed under the terms of the Creative Commons
Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/),
which permits use, sharing, adaptation, distribution and reproduction in any medium
or format, as long as you give appropriate credit to the original author(s) and the
source, provide a link to the Creative Commons license and indicate if changes were
made.
The images or other third party material in this chapter are included in the chapter’s
Creative Commons license, unless indicated otherwise in a credit line to the material. If
material is not included in the chapter’s Creative Commons license and your intended
use is not permitted by statutory regulation or exceeds the permitted use, you will need
to obtain permission directly from the copyright holder.
M. Mann and C. Barrett
30. Peled, D.: Verification for robust specification. In: Gunter, E.L., Felty, A. (eds.)
Theorem Proving in Higher Order Logics. pp. 231–241. Springer Berlin Heidelberg,
Berlin, Heidelberg (1997)
31. Peled, D.A., Wilke, T., Wolper, P.: An algorithmic approach for checking closure
properties of temporal logic specifications and omega-regular languages. Theor.
Comput. Sci. 195(2), 183–203 (1998)
32. Price, D.: Pentium fdiv flaw-lessons learned. IEEE Micro 15(2), 86–88 (April 1995).
https://doi.org/10.1109/40.372360
33. Sagstetter, F., Lukasiewycz, M., Steinhorst, S., Wolf, M., Bouard, A., R. Harris, W., Jha, S., Peyrin, T., Poschmann, A., Chakraborty, S.: Security challenges in automotive hardware/software architecture design. pp. 458–463 (01 2013).
https://doi.org/10.7873/DATE.2013.102
34. Shacham, O., Azizi, O., Wachs, M., Richardson, S., Horowitz, M.: Rethinking digital design: Why design must change. IEEE Micro 30(6), 9–24 (2010)
35. Strichman, O.: Tuning SAT checkers for bounded model checking. In: CAV. Lecture
Notes in Computer Science, vol. 1855, pp. 480–494. Springer (2000)
36. Strichman, O.: Accelerating bounded model checking of safety properties. Formal
Methods in System Design 24(1), 5–24 (2004)
37. Wang, C., Yang, Z., Kahlon, V., Gupta, A.: Peephole partial order reduction. In:
Ramakrishnan, C.R., Rehof, J. (eds.) Tools and Algorithms for the Construction
and Analysis of Systems. pp. 382–396. Springer Berlin Heidelberg, Berlin, Heidelberg (2008)
38. Wolf, C., Glaser, J., Kepler, J.: Yosys-a free Verilog synthesis suite. In: Proceedings
of the 21st Austrian Workshop on Microelectronics (Austrochip) (2013)
Open Access This chapter is licensed under the terms of the Creative Commons
Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/),
which permits use, sharing, adaptation, distribution and reproduction in any medium
or format, as long as you give appropriate credit to the original author(s) and the
source, provide a link to the Creative Commons license and indicate if changes were
made.
The images or other third party material in this chapter are included in the chapter’s
Creative Commons license, unless indicated otherwise in a credit line to the material. If
material is not included in the chapter’s Creative Commons license and your intended
use is not permitted by statutory regulation or exceeds the permitted use, you will need
to obtain permission directly from the copyright holder.