Partial Order Reduction for Deep Bug Finding in Synchronous Hardware
385
10. Bradley, A.R.: Sat-based model checking without unrolling. In: VMCAI. Lecture
Notes in Computer Science, vol. 6538, pp. 70–87. Springer (2011)
11. Brayton, R., Mishchenko, A.: Abc: An academic industrial-strength verification
tool. In: Touili, T., Cook, B., Jackson, P. (eds.) Computer Aided Verification. pp.
24–40. Springer Berlin Heidelberg, Berlin, Heidelberg (2010)
12. Burch, J., Clarke, E., McMillan, K., Dill, D., Hwang, L.: Symbolic model
checking: 1020 states and beyond. Information and Computation 98(2) (1992).
https://doi.org/https://doi.org/10.1016/0890-5401(92)90017-A
13. Clarke, E.M., Emerson, E.A., Jha, S., Sistla, A.P.: Symmetry reductions inmodel
checking. In: CAV. Lecture Notes in Computer Science, vol. 1427, pp. 147–158.
Springer (1998)
14. Clarke, Jr., E.M., Grumberg, O., Peled, D.A.: Model Checking. MIT Press, Cambridge, MA, USA (1999)
15. Clarke, E., Henzinger, T., Veith, H.: Handbook of Model Checking.
Springer International Publishing (2016), https://books.google.com/books?id=
qxG8oAEACAAJ
16. E´ en, N., Mishchenko, A., Brayton, R.K.: Efficient implementation of property directed reachability. In: FMCAD. pp. 125–134. FMCAD Inc. (2011)
17. Foster, H.: Applied assertion-based verification: An industry perspective. Foundations and Trends in Electronic Design Automation 3(1), 1–95 (2009)
18. Ganai, M.K., Gupta, A.: Accelerating high-level bounded model checking. In: ICCAD. pp. 794–801. ACM (2006)
19. Gupta, A., Ganai, M.K., Wang, C., Yang, Z., Ashar, P.: Learning from bdds in
sat-based bounded model checking. In: DAC. pp. 824–829. ACM (2003)
20. Johannsen, P.: Speeding Up Hardware Verification by Automated Data Path Scaling. Ph.D. thesis, University of Kiel (2002)
21. Kahlon, V., Wang, C., Gupta, A.: Monotonic partial order reduction: An optimal
symbolic partial order reduction technique. In: CAV. Lecture Notes in Computer
Science, vol. 5643, pp. 398–413. Springer (2009)
22. Kocher, P., Genkin, D., Gruss, D., Haas, W., Hamburg, M., Lipp, M., Mangard,
S., Prescher, T., Schwarz, M., Yarom, Y.: Spectre attacks: Exploiting speculative
execution. CoRR abs/1801.01203 (2018), http://arxiv.org/abs/1801.01203
23. Kroening, D., Strichman, O.: Decision Procedures: An Algorithmic Point of View.
Springer Publishing Company, Incorporated, 1 edn. (2008)
24. Lam, W.K.: Hardware Design Verification: Simulation and Formal Method-Based
Approaches (Prentice Hall Modern Semiconductor Design Series). Prentice Hall
PTR, Upper Saddle River, NJ, USA (2005)
25. Lipp, M., Schwarz, M., Gruss, D., Prescher, T., Haas, W., Mangard, S., Kocher, P.,
Genkin, D., Yarom, Y., Hamburg, M.: Meltdown. CoRR abs/1801.01207 (2018)
26. Mattarei, C., Mann, M., Barrett, C.W., Daly, R.G., Huff, D., Hanrahan, P.: Cosa:
Integrated verification for agile hardware design. In: FMCAD. pp. 1–5. IEEE (2018)
27. McMillan, K.L.: Interpolation and sat-based model checking. In: Hunt, W.A.,
Somenzi, F. (eds.) Computer Aided Verification. pp. 1–13. Springer Berlin Heidelberg, Berlin, Heidelberg (2003)
28. McMillan, K.L.: A methodology for hardware verification using compositional
model checking. Sci. Comput. Program. 37(1-3), 279–309 (2000)
29. Niemetz, A., Preiner, M., Wolf, C., Biere, A.: Btor2 , btormc and boolector 3.0. In:
CAV (1). Lecture Notes in Computer Science, vol. 10981, pp. 587–595. Springer
(2018)
385
10. Bradley, A.R.: Sat-based model checking without unrolling. In: VMCAI. Lecture
Notes in Computer Science, vol. 6538, pp. 70–87. Springer (2011)
11. Brayton, R., Mishchenko, A.: Abc: An academic industrial-strength verification
tool. In: Touili, T., Cook, B., Jackson, P. (eds.) Computer Aided Verification. pp.
24–40. Springer Berlin Heidelberg, Berlin, Heidelberg (2010)
12. Burch, J., Clarke, E., McMillan, K., Dill, D., Hwang, L.: Symbolic model
checking: 1020 states and beyond. Information and Computation 98(2) (1992).
https://doi.org/https://doi.org/10.1016/0890-5401(92)90017-A
13. Clarke, E.M., Emerson, E.A., Jha, S., Sistla, A.P.: Symmetry reductions inmodel
checking. In: CAV. Lecture Notes in Computer Science, vol. 1427, pp. 147–158.
Springer (1998)
14. Clarke, Jr., E.M., Grumberg, O., Peled, D.A.: Model Checking. MIT Press, Cambridge, MA, USA (1999)
15. Clarke, E., Henzinger, T., Veith, H.: Handbook of Model Checking.
Springer International Publishing (2016), https://books.google.com/books?id=
qxG8oAEACAAJ
16. E´ en, N., Mishchenko, A., Brayton, R.K.: Efficient implementation of property directed reachability. In: FMCAD. pp. 125–134. FMCAD Inc. (2011)
17. Foster, H.: Applied assertion-based verification: An industry perspective. Foundations and Trends in Electronic Design Automation 3(1), 1–95 (2009)
18. Ganai, M.K., Gupta, A.: Accelerating high-level bounded model checking. In: ICCAD. pp. 794–801. ACM (2006)
19. Gupta, A., Ganai, M.K., Wang, C., Yang, Z., Ashar, P.: Learning from bdds in
sat-based bounded model checking. In: DAC. pp. 824–829. ACM (2003)
20. Johannsen, P.: Speeding Up Hardware Verification by Automated Data Path Scaling. Ph.D. thesis, University of Kiel (2002)
21. Kahlon, V., Wang, C., Gupta, A.: Monotonic partial order reduction: An optimal
symbolic partial order reduction technique. In: CAV. Lecture Notes in Computer
Science, vol. 5643, pp. 398–413. Springer (2009)
22. Kocher, P., Genkin, D., Gruss, D., Haas, W., Hamburg, M., Lipp, M., Mangard,
S., Prescher, T., Schwarz, M., Yarom, Y.: Spectre attacks: Exploiting speculative
execution. CoRR abs/1801.01203 (2018), http://arxiv.org/abs/1801.01203
23. Kroening, D., Strichman, O.: Decision Procedures: An Algorithmic Point of View.
Springer Publishing Company, Incorporated, 1 edn. (2008)
24. Lam, W.K.: Hardware Design Verification: Simulation and Formal Method-Based
Approaches (Prentice Hall Modern Semiconductor Design Series). Prentice Hall
PTR, Upper Saddle River, NJ, USA (2005)
25. Lipp, M., Schwarz, M., Gruss, D., Prescher, T., Haas, W., Mangard, S., Kocher, P.,
Genkin, D., Yarom, Y., Hamburg, M.: Meltdown. CoRR abs/1801.01207 (2018)
26. Mattarei, C., Mann, M., Barrett, C.W., Daly, R.G., Huff, D., Hanrahan, P.: Cosa:
Integrated verification for agile hardware design. In: FMCAD. pp. 1–5. IEEE (2018)
27. McMillan, K.L.: Interpolation and sat-based model checking. In: Hunt, W.A.,
Somenzi, F. (eds.) Computer Aided Verification. pp. 1–13. Springer Berlin Heidelberg, Berlin, Heidelberg (2003)
28. McMillan, K.L.: A methodology for hardware verification using compositional
model checking. Sci. Comput. Program. 37(1-3), 279–309 (2000)
29. Niemetz, A., Preiner, M., Wolf, C., Biere, A.: Btor2 , btormc and boolector 3.0. In:
CAV (1). Lecture Notes in Computer Science, vol. 10981, pp. 587–595. Springer
(2018)