programmability. Programmability can be maintained without large memory cells by
using atomic switches. The reconfigurable architecture exploiting high level behavioral synthesis technology and atomic switches enable efficient implementations and
high performance for edge computing of IoT applications. The architecture is an
embodiment of what we call an Embedded Automaton (EA) [16]. Notwithstanding
its low power consumption characteristics, dynamically reconfigurable architecture
does not eliminate configuration memories in itself [18, 19]. Physical improvement
is required to eliminate those volatile memories. We considered complementary
atom switch (CAS) and the FPGA architecture using CAS [20–23] to establish an
architecture for dynamically reconfigurable processor element (PE) with atomic
switches [24]. We call the architecture Generic Processing Architecture (GPE).
GPE is a natural implementation of processor element using atomic switches, and
it is explained in the next section.
4 Adopting Atomic Switch FPGA to Embedded Automaton
This section presents a four-layer architecture for implementing Embedded Automaton (EA) that is mentioned in the previous section using atomic switches. The design
flow considered here aims at designing onboard equipment of space systems.
Dependability is a mandatory requirement for this application, and hence the reliability design must be included in the design flow.
4.1 Associating Layered Structure Design of a PE
with Atomic Switch FPGA
We proposed a four-layered architecture to design a PE using atomic switch FPGA
[2, 16, 25]. It is called “Generic Processor element (GPE) architecture”. Each layer
corresponds to I/O layer, fine grained layer, coarse grained layer and switch layer,
from the bottom to the top, respectively. These layers are shown in Fig. 10 [2]. The
bottom layer is I/O interface circuitry. It is implemented with random logic primitives and mixed signal I/O circuitries. The fine grained layer mainly consists of finite
state machines and data paths. They are replaceable to follow the context described
by high-level languages. This layer includes Look-Up Tables (LUTs). LUTs are
used to configure data paths and finite state machines. The coarse grained layer is
located on the fine grained layer. This layer includes operation units like Arithmetic
and Logic Units (ALUs). The function of an operation unit defined in the coarse
grained layer corresponds to an instruction set of a conventional MCU.
I/O blocks, fine grained function blocks, and coarse grained function blocks are
connected to each other on the topmost layer “switch layer”.
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H. Hihara et al.
using atomic switches. The reconfigurable architecture exploiting high level behavioral synthesis technology and atomic switches enable efficient implementations and
high performance for edge computing of IoT applications. The architecture is an
embodiment of what we call an Embedded Automaton (EA) [16]. Notwithstanding
its low power consumption characteristics, dynamically reconfigurable architecture
does not eliminate configuration memories in itself [18, 19]. Physical improvement
is required to eliminate those volatile memories. We considered complementary
atom switch (CAS) and the FPGA architecture using CAS [20–23] to establish an
architecture for dynamically reconfigurable processor element (PE) with atomic
switches [24]. We call the architecture Generic Processing Architecture (GPE).
GPE is a natural implementation of processor element using atomic switches, and
it is explained in the next section.
4 Adopting Atomic Switch FPGA to Embedded Automaton
This section presents a four-layer architecture for implementing Embedded Automaton (EA) that is mentioned in the previous section using atomic switches. The design
flow considered here aims at designing onboard equipment of space systems.
Dependability is a mandatory requirement for this application, and hence the reliability design must be included in the design flow.
4.1 Associating Layered Structure Design of a PE
with Atomic Switch FPGA
We proposed a four-layered architecture to design a PE using atomic switch FPGA
[2, 16, 25]. It is called “Generic Processor element (GPE) architecture”. Each layer
corresponds to I/O layer, fine grained layer, coarse grained layer and switch layer,
from the bottom to the top, respectively. These layers are shown in Fig. 10 [2]. The
bottom layer is I/O interface circuitry. It is implemented with random logic primitives and mixed signal I/O circuitries. The fine grained layer mainly consists of finite
state machines and data paths. They are replaceable to follow the context described
by high-level languages. This layer includes Look-Up Tables (LUTs). LUTs are
used to configure data paths and finite state machines. The coarse grained layer is
located on the fine grained layer. This layer includes operation units like Arithmetic
and Logic Units (ALUs). The function of an operation unit defined in the coarse
grained layer corresponds to an instruction set of a conventional MCU.
I/O blocks, fine grained function blocks, and coarse grained function blocks are
connected to each other on the topmost layer “switch layer”.
46
H. Hihara et al.