Secondly, video rate signal processing throughput is required. An embedded processor element should be capable of processing sensor signals at video rate to
eliminate large main memory cells for application programs and large frame memory
buffers. One processor should be capable of processing signals from at least one
channel. If a processor element can process signals in video rate without using large
program memories, we can put one processor element in on one channel, and it is
also possible to reduce buffer memory capacity. Thirdly, programming flexibility
during the development phase is mandatory for the compensation of detector
characteristics. Several kinds of compensation are required for image sensors to
enhance dynamic range and/or to normalization. A compensation for a degraded
sensing device is also necessary sometimes. Programming capability with high-level
programming languages (ex. C language) is anticipated because simulation is a
mandatory process for designing onboard sensors. The fourth requirement is reliability, because sensing devices and even edge computing nodes are place in harsh
environment in the field.
As for the first requirement, we can exploit the characteristics of embedded
application systems to reduce memory related circuitries [16]. Implementing applications as hardware logic, instead of processors with stored memory architecture,
does not affect the productivity, while flexibility is required on the development
environment.
A dynamically reconfigurable architecture is a proper solution for the issue. It is
reported that power consumption of a dynamically reconfigurable processor (DRP)
was one hundredth for the same amount of operations compared to a conventional
microprocessor based on stored program architecture [5]. High level and behavioral
synthesis technology can be used for the application development using DRPs
[5, 16]. Operation efficiency is much improved compared to conventional software
compilation for fixed ISP hardware of MCUs. Atomic switches exploit the merit of
DRPs and high level and behavioral synthesis technologies to reduce power consumption and resources. In consequence, significant improvement of footprint and
power efficiency is expected.
Once the first requirement is satisfied, solutions for the requirement contributes to
fulfill the second requirement. Customized hardware can be implemented on ASICs
augmented by atomic switches. Customization is possible to ASICs without affecting efficiency by using atomic switches. This feature enables processor elements to
process signals transmitted through more than or equal to one sensor signal channel.
As for the third requirement, it is necessary for developing embedded processor
applications to compensate for the sensing device characteristics, and development
efficiency should be maintained. We consider the framework of overall signal
processing chain and refer IoT five-layer architecture model [17] as shown in
Fig. 9 to realize development efficiency. IoT is not merely regarded as a collection
system of sensor data and analysis results. Flexibility, robustness to change, and the
ability to maintain the accuracy across the entire system are the key features of the
IoT five-layer architecture model. Moreover, the introduction of the layered concept
improves the connectivity with other systems. The gradual growth of the system is
supported and the means of creating new values can be provided by making it easier
44
H. Hihara et al.
eliminate large main memory cells for application programs and large frame memory
buffers. One processor should be capable of processing signals from at least one
channel. If a processor element can process signals in video rate without using large
program memories, we can put one processor element in on one channel, and it is
also possible to reduce buffer memory capacity. Thirdly, programming flexibility
during the development phase is mandatory for the compensation of detector
characteristics. Several kinds of compensation are required for image sensors to
enhance dynamic range and/or to normalization. A compensation for a degraded
sensing device is also necessary sometimes. Programming capability with high-level
programming languages (ex. C language) is anticipated because simulation is a
mandatory process for designing onboard sensors. The fourth requirement is reliability, because sensing devices and even edge computing nodes are place in harsh
environment in the field.
As for the first requirement, we can exploit the characteristics of embedded
application systems to reduce memory related circuitries [16]. Implementing applications as hardware logic, instead of processors with stored memory architecture,
does not affect the productivity, while flexibility is required on the development
environment.
A dynamically reconfigurable architecture is a proper solution for the issue. It is
reported that power consumption of a dynamically reconfigurable processor (DRP)
was one hundredth for the same amount of operations compared to a conventional
microprocessor based on stored program architecture [5]. High level and behavioral
synthesis technology can be used for the application development using DRPs
[5, 16]. Operation efficiency is much improved compared to conventional software
compilation for fixed ISP hardware of MCUs. Atomic switches exploit the merit of
DRPs and high level and behavioral synthesis technologies to reduce power consumption and resources. In consequence, significant improvement of footprint and
power efficiency is expected.
Once the first requirement is satisfied, solutions for the requirement contributes to
fulfill the second requirement. Customized hardware can be implemented on ASICs
augmented by atomic switches. Customization is possible to ASICs without affecting efficiency by using atomic switches. This feature enables processor elements to
process signals transmitted through more than or equal to one sensor signal channel.
As for the third requirement, it is necessary for developing embedded processor
applications to compensate for the sensing device characteristics, and development
efficiency should be maintained. We consider the framework of overall signal
processing chain and refer IoT five-layer architecture model [17] as shown in
Fig. 9 to realize development efficiency. IoT is not merely regarded as a collection
system of sensor data and analysis results. Flexibility, robustness to change, and the
ability to maintain the accuracy across the entire system are the key features of the
IoT five-layer architecture model. Moreover, the introduction of the layered concept
improves the connectivity with other systems. The gradual growth of the system is
supported and the means of creating new values can be provided by making it easier
44
H. Hihara et al.