The clear desire for neuromorphic architectures has led to further investigation
and developments of different synthetic synapse models. In recent years, atomic
switch systems have garnered much interest and are now being modeled and
investigated as synthetic synapses with the hopes of scaling them into a connected
network yielding synaptic densities and topographies similar to that of the human
brain.
ASICs
Carver Mead’s work in pioneering analog VLSI implementations for neural systems
set the foundation for early neurocomputing architectures, or neuroarchitectures. His
work clearly outlined the need for neurons and synapses (weighted connections
between neurons) for real-time processing on a single device capable of parallel
processing. Mead’s investigation of neural networks denoted that various frameworks could be implemented for general purpose neurocomputers, however, the
neuroarchitecture will need to be uniquely designed while accommodating the
desired neural networks [7]. This presents the potential to develop rigid and highly
efficient task specific neurocomputers or, by contrast, versatile and tunable
neurocomputers utilizing a hierarchy of neural networks.
Early implementations of neurocomputers were achieved using applicationspecific integrated circuits (ASICs) fabricated using CMOS VLSI technology. As
their name suggests, they were developed for the execution of specific tasks and
cannot be reconfigured at a later time by the end user. Each ASIC works as either as a
master or slave node interconnected in a ring or bus network which broadcast signals
based on their topology. The master node functions to control neurocomputation
while the slave nodes enable parallel processing, the backbone of ASIC’s efficiency
for neuroarchitectures. This system utilizes external memory for the storage of
neuron outputs and synaptic weights [32]. Efficiency and speed is ultimately
governed by the number of neurons on a chip. An issue with ASIC
neuroarchitectures is that they are developed for a specific neural network and are
not reconfigurable devices [33] despite this they are notably proficient at specific
tasks and highly power efficient.
3.2 FPGAs
Field-programmable gate arrays (FPGAs) while worse in raw performance than
ASICs, offer the added benefit of reconfigurability. FPGAs are designed to be
manipulated by the end user allowing for a great degree of flexibility in designing
FPGA based neuroarchitectures capable of functioning in an array of neural networks for prospective optimization in ASIC implementations. Despite their lower
performance, FPGA’s re-configurability and capacity to perform parallel processing
has overshadowed ASICs in the development of neurocomputers [33].
As FPGA architectures continue to garner interest, programming frameworks
have been developed to simplify their manipulation. The Open Computing
210
R. Aguilera et al.
and developments of different synthetic synapse models. In recent years, atomic
switch systems have garnered much interest and are now being modeled and
investigated as synthetic synapses with the hopes of scaling them into a connected
network yielding synaptic densities and topographies similar to that of the human
brain.
ASICs
Carver Mead’s work in pioneering analog VLSI implementations for neural systems
set the foundation for early neurocomputing architectures, or neuroarchitectures. His
work clearly outlined the need for neurons and synapses (weighted connections
between neurons) for real-time processing on a single device capable of parallel
processing. Mead’s investigation of neural networks denoted that various frameworks could be implemented for general purpose neurocomputers, however, the
neuroarchitecture will need to be uniquely designed while accommodating the
desired neural networks [7]. This presents the potential to develop rigid and highly
efficient task specific neurocomputers or, by contrast, versatile and tunable
neurocomputers utilizing a hierarchy of neural networks.
Early implementations of neurocomputers were achieved using applicationspecific integrated circuits (ASICs) fabricated using CMOS VLSI technology. As
their name suggests, they were developed for the execution of specific tasks and
cannot be reconfigured at a later time by the end user. Each ASIC works as either as a
master or slave node interconnected in a ring or bus network which broadcast signals
based on their topology. The master node functions to control neurocomputation
while the slave nodes enable parallel processing, the backbone of ASIC’s efficiency
for neuroarchitectures. This system utilizes external memory for the storage of
neuron outputs and synaptic weights [32]. Efficiency and speed is ultimately
governed by the number of neurons on a chip. An issue with ASIC
neuroarchitectures is that they are developed for a specific neural network and are
not reconfigurable devices [33] despite this they are notably proficient at specific
tasks and highly power efficient.
3.2 FPGAs
Field-programmable gate arrays (FPGAs) while worse in raw performance than
ASICs, offer the added benefit of reconfigurability. FPGAs are designed to be
manipulated by the end user allowing for a great degree of flexibility in designing
FPGA based neuroarchitectures capable of functioning in an array of neural networks for prospective optimization in ASIC implementations. Despite their lower
performance, FPGA’s re-configurability and capacity to perform parallel processing
has overshadowed ASICs in the development of neurocomputers [33].
As FPGA architectures continue to garner interest, programming frameworks
have been developed to simplify their manipulation. The Open Computing
210
R. Aguilera et al.