produce a desired output function. Another problem of these early attempts was the
lack of scalability, and thus the difficulty to obtain more complex functions.
3 Hardware Paradigms for Neuromorphic Computing
The previous section described a few framework paradigms for next-generation
computing. This section will discuss several examples of the physical implementation of these paradigms, including hardware configurations utilized for deep learning
and neuromorphic computing. Throughout the design of a new architecture, its
desired neuromorphic properties need to be considered. An array of different metrics
can benchmark devices for the implementation of a specific neural network. Considerable factors include efficiency, reconfigurability, and scalability.
3.1 Neuromorphic Chips
Neuromorphic refers to any artificial neural system whose core design and architectures are based upon the biological central nervous systems. Traditional computing
architecture efficiency is governed by how many floating-point operations per
second (FLOPS) per watt can be performed. In developing neuromorphic systems,
spiking neurons are fabricated into the hardware; these can be benchmarked by their
synaptic operations per second (SOPS) per watt [30]. Floating-point operations are
inefficient and slow; even the most powerful super-computers are not capable of
obtaining real-time performance on detailed large-scale simulations of neural systems [30]. Synaptic operations offer an advantage in that operations are achieved
directly through the hardware; this allows for real-time operation independent of
synapse density and/or coupling. This advantage is achieved through circumventing
the von Neumann bottleneck; a single component of hardware running specific tasks
alleviates the overhead from multiple components communicating with each other
achieving real-time analysis.
Silicon neurons are a promising avenue for mimicking biological synaptic/neuronal interactions. Unlike the previously mentioned hardware, a silicon neuron can
be broken into computational blocks which can be functionalized for task specific
neuronal activity. The synaptic block is capable of carrying out both linear and
non-linear input spikes with short and long-term plasticity mechanisms available.
Some blocks are a group of sub-blocks designed to computationally represent the
theoretical model in which they are based upon. Finally, dendrite and axon circuit
blocks account for the spatial structure and interconnectivity of the overall system
allowing for an intricate and fully connected array of neurons [31]. Sub-segments of
each element can be manipulated for the desired implementation of a specific task or
model.
Atomic Switch Networks for Neuroarchitectonics: Past, Present, Future
209
lack of scalability, and thus the difficulty to obtain more complex functions.
3 Hardware Paradigms for Neuromorphic Computing
The previous section described a few framework paradigms for next-generation
computing. This section will discuss several examples of the physical implementation of these paradigms, including hardware configurations utilized for deep learning
and neuromorphic computing. Throughout the design of a new architecture, its
desired neuromorphic properties need to be considered. An array of different metrics
can benchmark devices for the implementation of a specific neural network. Considerable factors include efficiency, reconfigurability, and scalability.
3.1 Neuromorphic Chips
Neuromorphic refers to any artificial neural system whose core design and architectures are based upon the biological central nervous systems. Traditional computing
architecture efficiency is governed by how many floating-point operations per
second (FLOPS) per watt can be performed. In developing neuromorphic systems,
spiking neurons are fabricated into the hardware; these can be benchmarked by their
synaptic operations per second (SOPS) per watt [30]. Floating-point operations are
inefficient and slow; even the most powerful super-computers are not capable of
obtaining real-time performance on detailed large-scale simulations of neural systems [30]. Synaptic operations offer an advantage in that operations are achieved
directly through the hardware; this allows for real-time operation independent of
synapse density and/or coupling. This advantage is achieved through circumventing
the von Neumann bottleneck; a single component of hardware running specific tasks
alleviates the overhead from multiple components communicating with each other
achieving real-time analysis.
Silicon neurons are a promising avenue for mimicking biological synaptic/neuronal interactions. Unlike the previously mentioned hardware, a silicon neuron can
be broken into computational blocks which can be functionalized for task specific
neuronal activity. The synaptic block is capable of carrying out both linear and
non-linear input spikes with short and long-term plasticity mechanisms available.
Some blocks are a group of sub-blocks designed to computationally represent the
theoretical model in which they are based upon. Finally, dendrite and axon circuit
blocks account for the spatial structure and interconnectivity of the overall system
allowing for an intricate and fully connected array of neurons [31]. Sub-segments of
each element can be manipulated for the desired implementation of a specific task or
model.
Atomic Switch Networks for Neuroarchitectonics: Past, Present, Future
209