List of Figures
Fig. 2.1 CMOS and TFET transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Fig. 2.2 Schematic representation of the energy-band diagrams for
NTFET. OFF state: V D = 1 V, V G = 0 V-black curves; ON
state: V D = 1 V, V G = 1.6 V-red curves . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Fig. 2.3 TFET and MOSFET I D = f (V G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Fig. 2.4 Ambipolar effect: TFET conducts for both positive and
negative V G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Fig. 2.5 TFET I D in reverse bias, V DS < 0 V, V G = 0.25–1.5 V . . . . . . . . . .
8
Fig. 2.6 Schematic representation of the simulated DG TFET
structure with low-k spacer and high-k gate dielectrics [1] . . . . . . . .
9
Fig. 2.7 32 nm TFET and PTM MOSFET I D (V GS ); V DS step:
0.25 V [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Fig. 2.8 Output characteristics of the TFET for forward biasing;
I D (V DS ) [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Fig. 2.9 Output characteristics of the TFET for reverse biasing;
I D (V DS ) step: 0.25 V [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Fig. 2.10 Total Gate Capacitance of a PMOS (solid lines) and PTFET
(dotted lines) as a function of gate voltage for different drain
voltage values; V DS step: 0.25 V [©2016 IEEE] . . . . . . . . . . . . . . . . . . . 11
Fig. 2.11 Frequency vs. supply voltage for TFET and PTM [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fig. 2.12 Power delay product (PDP) of the TFET and PTM [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fig. 2.13 The result of the nine-stage RO simulation performed using
TFETs at V DD = 1 V [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fig. 2.14 Dynamic and static power vs. supply voltage for TFET and
CMOS PTM [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Fig. 2.15 P dyn /P stat of a nine stage TFET and CMOS RO . . . . . . . . . . . . . . . . . . 14
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