8.1 TFET-CMOS Hybrid Cores
125
maximize the use of TFET cores for energy efficiency. The presented results show
up to 30% leakage and 17% dynamic power savings with a performance degradation
of only 1%. However, in the proposed system, either CMOS cores or TFET cores
are unused at any given point of time resulting in unused silicon footprint and area,
which leads to increased cost of the system. Assuming the same size of the cores,
50% silicon area will be unused at any given point of time. In addition, due to higher
than CMOS C GD , the dynamic power consumption of TFET cores will be higher
than CMOS for the same voltage of operation, which reduces the gain in dynamic
power consumption significantly.
A major improvement to existing art would be a tighter cointegration of TFET
and CMOS components. It was demonstrated in this book that exploiting the NDR
property of Si-TFETs, low-leakage, high-performance memories, and flip-flops are
achievable. In a hybrid TFET-CMOS core it would be therefore beneficial to share
TFET memories, SRAM, and uDRAM if necessary, between TFET and CMOS
cores and reuse TFET flip-flops in both.
Another dimension of a hybrid system involves an even tighter cointegration of
TFET and CMOS within the system. Provided the TFET and CMOS standard cells
can be cointegrated in the same design with no or low area overhead it would be
possible to design full TFET-CMOS hybrid cores. Even if only a reduced set of
TFET standard cells with full timing specification is provided to the synthesis and
place-and-route EDA tools, the software itself will be able to decide which type
of cell to use in different parts of the logic block. This could result, for example,
in the clock tree being implemented using fast and low PDP CMOS gates while
large parts of the remaining blocks being designed with TFETs in order to keep the
static power low. Such a system together with TFET memories could be a powerful
solution for many applications since it should provide sufficiently high operating
frequency coupled with extremely low standby power due to low-leakage memories
and the fact that the logic core can be fully power-gated if necessary. Flip-flops can
be kept on the secondary power grid and kept powered up even during standby in
the event where their states have to be maintained; this would come at a certain area
cost. Even in this situation, however, their contribution to the leakage power remains
negligible (see Chap. 5) since these flip-flops are TFET based. It should also be
noted that this kind of hybrid system could operate at a nominal voltage since there
is no need for different voltage domains for dual-rail memory management, as is
typically the case in many modern applications. This simplifies the power routing
and reduces area footprint and power consumption relative to the use of DC–DC
converters.
There are multiple challenges that would have to be addressed delivering the
above scenario. First is the design and full characterization of all the standard cells
and memory IPs required for the implementation of such a system. Next would
be the cointegration with different types of existing devices and benchmarking the
125
maximize the use of TFET cores for energy efficiency. The presented results show
up to 30% leakage and 17% dynamic power savings with a performance degradation
of only 1%. However, in the proposed system, either CMOS cores or TFET cores
are unused at any given point of time resulting in unused silicon footprint and area,
which leads to increased cost of the system. Assuming the same size of the cores,
50% silicon area will be unused at any given point of time. In addition, due to higher
than CMOS C GD , the dynamic power consumption of TFET cores will be higher
than CMOS for the same voltage of operation, which reduces the gain in dynamic
power consumption significantly.
A major improvement to existing art would be a tighter cointegration of TFET
and CMOS components. It was demonstrated in this book that exploiting the NDR
property of Si-TFETs, low-leakage, high-performance memories, and flip-flops are
achievable. In a hybrid TFET-CMOS core it would be therefore beneficial to share
TFET memories, SRAM, and uDRAM if necessary, between TFET and CMOS
cores and reuse TFET flip-flops in both.
Another dimension of a hybrid system involves an even tighter cointegration of
TFET and CMOS within the system. Provided the TFET and CMOS standard cells
can be cointegrated in the same design with no or low area overhead it would be
possible to design full TFET-CMOS hybrid cores. Even if only a reduced set of
TFET standard cells with full timing specification is provided to the synthesis and
place-and-route EDA tools, the software itself will be able to decide which type
of cell to use in different parts of the logic block. This could result, for example,
in the clock tree being implemented using fast and low PDP CMOS gates while
large parts of the remaining blocks being designed with TFETs in order to keep the
static power low. Such a system together with TFET memories could be a powerful
solution for many applications since it should provide sufficiently high operating
frequency coupled with extremely low standby power due to low-leakage memories
and the fact that the logic core can be fully power-gated if necessary. Flip-flops can
be kept on the secondary power grid and kept powered up even during standby in
the event where their states have to be maintained; this would come at a certain area
cost. Even in this situation, however, their contribution to the leakage power remains
negligible (see Chap. 5) since these flip-flops are TFET based. It should also be
noted that this kind of hybrid system could operate at a nominal voltage since there
is no need for different voltage domains for dual-rail memory management, as is
typically the case in many modern applications. This simplifies the power routing
and reduces area footprint and power consumption relative to the use of DC–DC
converters.
There are multiple challenges that would have to be addressed delivering the
above scenario. First is the design and full characterization of all the standard cells
and memory IPs required for the implementation of such a system. Next would
be the cointegration with different types of existing devices and benchmarking the