124
8 Perspective
compatible with current CMOS processes and can have reasonable production yield.
Moreover, since these devices are purely silicon based, on-chip cointegration with
standard CMOS devices is possible.
In recent years the market of battery-powered devices has been experiencing
year-to-year exponential growth, a trend that is expected to continue. Within
this market there are many devices, different kinds of sensors, for example, that
are event-triggered with long standby cycles and have low operating frequency
requirements while active. The standard approach to address this operating mode
is to introduce sleep intervals for memories where the periphery is power gated
and bitcell arrays are kept at scaled down supply voltages. The gains offered by
this technique are, however, limited, moreover they introduce additional design and
timing complexity and the requirement to generate and maintain additional supply
voltage levels. Another solution consists in the use of non-volatile devices, such as
RRAM, PCM, MRAM, etc., which maintain data even if the memory is completely
powered down. The problem with this approach is that non-volatile devices suffer
from a range of problems like the limited production yield, low endurance, high
variability (also cycle-to-cycle), high programming currents, low performance, etc.,
placing them in the memory hierarchy somewhere between DRAM and Flash, rather
than replacing SRAMs.
In battery-powered applications TFETs are an obvious match since the extremely
low leakage with reduced drive current fits the requirements perfectly. Moreover,
sensor-node designs are highly area constrained as the cost is one of the key
concerns. It was demonstrated that TFETs can be competitive or superior even in
that regard either by the use of a standard 6T-SRAM-bitcell based design or with
the more advanced designs such as the 3T SRAM (see Chap. 3) or the uDRAMbased 2T1C SRAM (see Chap. 4). With the use of the TFET Flip-flop (see Chap. 5)
and having designed a set of TFET standard cells a full Si-TFET SoC can be built.
Given the properties of the device, this can be a perfect solution for systems where
leakage and area are targeted with lower performance (in the range of tens of MHz)
at nominal voltage, as is the case for many sensor-node applications.
Medium-to-high performance, low leakage, and low energy pure Si-TFET cores
are, however, challenging. As detailed in Chap. 2, TFETs exhibit rather poor PDP
and suffer in performance from device stacking due to high I D (V DS ) dependence,
making logic gates with a few transistors stacked between power and ground very
slow. It was demonstrated though, that memories and flip-flops can be designed in
a way, which provides high frequency and low leakage, even though the standardcell logic might be a bottleneck. One of the solutions to the problem is to design
hybrid TFET-CMOS cores. In [4] a hybrid TFET-CMOS multi-core processor
is presented using CMOS cores for higher voltage and TFET cores for lower
voltage of operation. This is done to optimize energy efficiencies based on the
computation loads. Presented results show a 50% energy benefit and 25% energydelay product (EDP) benefit with single-threaded applications and up to 55%
EDP benefit with multi-threaded applications. Various benchmarks were run for
evaluating the performance. In [5], EDP-aware and barrier-aware DVFS is used to
8 Perspective
compatible with current CMOS processes and can have reasonable production yield.
Moreover, since these devices are purely silicon based, on-chip cointegration with
standard CMOS devices is possible.
In recent years the market of battery-powered devices has been experiencing
year-to-year exponential growth, a trend that is expected to continue. Within
this market there are many devices, different kinds of sensors, for example, that
are event-triggered with long standby cycles and have low operating frequency
requirements while active. The standard approach to address this operating mode
is to introduce sleep intervals for memories where the periphery is power gated
and bitcell arrays are kept at scaled down supply voltages. The gains offered by
this technique are, however, limited, moreover they introduce additional design and
timing complexity and the requirement to generate and maintain additional supply
voltage levels. Another solution consists in the use of non-volatile devices, such as
RRAM, PCM, MRAM, etc., which maintain data even if the memory is completely
powered down. The problem with this approach is that non-volatile devices suffer
from a range of problems like the limited production yield, low endurance, high
variability (also cycle-to-cycle), high programming currents, low performance, etc.,
placing them in the memory hierarchy somewhere between DRAM and Flash, rather
than replacing SRAMs.
In battery-powered applications TFETs are an obvious match since the extremely
low leakage with reduced drive current fits the requirements perfectly. Moreover,
sensor-node designs are highly area constrained as the cost is one of the key
concerns. It was demonstrated that TFETs can be competitive or superior even in
that regard either by the use of a standard 6T-SRAM-bitcell based design or with
the more advanced designs such as the 3T SRAM (see Chap. 3) or the uDRAMbased 2T1C SRAM (see Chap. 4). With the use of the TFET Flip-flop (see Chap. 5)
and having designed a set of TFET standard cells a full Si-TFET SoC can be built.
Given the properties of the device, this can be a perfect solution for systems where
leakage and area are targeted with lower performance (in the range of tens of MHz)
at nominal voltage, as is the case for many sensor-node applications.
Medium-to-high performance, low leakage, and low energy pure Si-TFET cores
are, however, challenging. As detailed in Chap. 2, TFETs exhibit rather poor PDP
and suffer in performance from device stacking due to high I D (V DS ) dependence,
making logic gates with a few transistors stacked between power and ground very
slow. It was demonstrated though, that memories and flip-flops can be designed in
a way, which provides high frequency and low leakage, even though the standardcell logic might be a bottleneck. One of the solutions to the problem is to design
hybrid TFET-CMOS cores. In [4] a hybrid TFET-CMOS multi-core processor
is presented using CMOS cores for higher voltage and TFET cores for lower
voltage of operation. This is done to optimize energy efficiencies based on the
computation loads. Presented results show a 50% energy benefit and 25% energydelay product (EDP) benefit with single-threaded applications and up to 55%
EDP benefit with multi-threaded applications. Various benchmarks were run for
evaluating the performance. In [5], EDP-aware and barrier-aware DVFS is used to