322
9 OBDH Technology of Lunar Lander
(1) Reading configuration data for comparison was to read data of configuration register inside FPGA through chip reading mode, and compare the data
with internal configuration data of chip or original configuration data by data
compare device outside the chip. The FPGA would be configured all or partially
after the error is found.
The main feature of this method was that the logical fault in FPGA can be repaired
purposefully and normal operation of FPGA would not be interrupted as well as
interruption of the device operation, which could hardly influence on the system.
However, additional hardware support was necessary such as peripheral control
circuits, computers, configuration data memory and etc.
(2) Periodic or command controlled reload was to reconfigure internal logic of
FPGA to correct possible SEU errors. This method did not need a lot of
additional hardware support. The FPGA configuration data was not required
to be read and judged before the logical refresh, so the design was simple.
Reload time could be determined according to requirement or reload could be
implemented by command control.
However, the disadvantage of this method was that normal operation of FPGA would
be interrupted during the configuration process, which would have a negative impact
on system operation. It could be loaded when there was no task or interruption was
acceptable according to requirements of operation mode. For example, the DMU
should be reloaded before the payload was powered on to ensure that the task could
be performed normally.
(3) The triple-mode redundancy was a SEU mitigation method. In the FPGA
design, all the functional units and circuits of logic circuit were duplicated
three times, and then the output of three circuits was passed through the decision circuit as the final output, and all logic was implemented by one FPGA
chip. This design method would bring more than 3 times consumption of logical
resources. If one of three circuits had a SEU error, the other two could still
output correct logical value, and the entire circuit could still maintain the correct
output through the majority of three circuits. From above analysis, it could be
seen that TMR technology could make FPGA obtain a single SEU immunity.
The basic architecture of TMR is shown in Fig. 9.5.
A lot of FPGA integrated circuits design for miniaturization was applied in OBDH
devices of the Chang’E-3 lunar lander. The relatively simple and key circuits were
mostly anti-fuse type FPGA, for example, telecommand decoding circuits. For
circuits with more complicated logic, large scale FPGA parts based on SRAM technology were selected and combined with corresponding anti-SEU measures such as
multiplexing and memory circuits according to practical applications and hardware
support conditions.
9 OBDH Technology of Lunar Lander
(1) Reading configuration data for comparison was to read data of configuration register inside FPGA through chip reading mode, and compare the data
with internal configuration data of chip or original configuration data by data
compare device outside the chip. The FPGA would be configured all or partially
after the error is found.
The main feature of this method was that the logical fault in FPGA can be repaired
purposefully and normal operation of FPGA would not be interrupted as well as
interruption of the device operation, which could hardly influence on the system.
However, additional hardware support was necessary such as peripheral control
circuits, computers, configuration data memory and etc.
(2) Periodic or command controlled reload was to reconfigure internal logic of
FPGA to correct possible SEU errors. This method did not need a lot of
additional hardware support. The FPGA configuration data was not required
to be read and judged before the logical refresh, so the design was simple.
Reload time could be determined according to requirement or reload could be
implemented by command control.
However, the disadvantage of this method was that normal operation of FPGA would
be interrupted during the configuration process, which would have a negative impact
on system operation. It could be loaded when there was no task or interruption was
acceptable according to requirements of operation mode. For example, the DMU
should be reloaded before the payload was powered on to ensure that the task could
be performed normally.
(3) The triple-mode redundancy was a SEU mitigation method. In the FPGA
design, all the functional units and circuits of logic circuit were duplicated
three times, and then the output of three circuits was passed through the decision circuit as the final output, and all logic was implemented by one FPGA
chip. This design method would bring more than 3 times consumption of logical
resources. If one of three circuits had a SEU error, the other two could still
output correct logical value, and the entire circuit could still maintain the correct
output through the majority of three circuits. From above analysis, it could be
seen that TMR technology could make FPGA obtain a single SEU immunity.
The basic architecture of TMR is shown in Fig. 9.5.
A lot of FPGA integrated circuits design for miniaturization was applied in OBDH
devices of the Chang’E-3 lunar lander. The relatively simple and key circuits were
mostly anti-fuse type FPGA, for example, telecommand decoding circuits. For
circuits with more complicated logic, large scale FPGA parts based on SRAM technology were selected and combined with corresponding anti-SEU measures such as
multiplexing and memory circuits according to practical applications and hardware
support conditions.