9.4 Design Methodology
321
3. Anti-SEU Design of FPGA Chip
The development of microelectronics technology had created a good opportunity for
solving problems. FPGA was favored by aerospace designers for their high functional
density, small size, low power consumption, and semi-customized flexible configuration capabilities. Different types of FPGA chips had been widely used in Chinese
aerospace electronics products. The main reason was that user’s requirement for
spacecraft technology was improved, and onboard devices should have advantages
of high functionality, small size, light weight, and low power consumption, at the
same time, some functions could not be realized by general IC or computer software.
In addition, some new technologies and user requirements were difficult to be quickly
solidified, and technical solutions could only be determined through repeated trials
and technical coordination between users and contractors. So the project designer
could only use a powerful, flexible and convenient FPGA to develop the prototype.
Furthermore, once the project had been initiated, the FPGA application had become
a final decision. ASIC was certainly one of the important approaches of miniaturization, but its full custom development model that could not be flexibly modified was
difficult to adapt to the development requirement of new device.
There were currently two popular types of FPGA architecture: one was based on
SRAM and another was anti-fuse FPGA.
The anti-fuse type FPGA had the ability to resist Single Event Upset (SEU). By
permanent internal connection and program, the internal logic of chip could only
be burned once. After being programmed, the logic could not be changed and there
was no memory configured. Therefore, its anti-SEU performance was better than
that based on SRAM, and it was unnecessary to be configured with PROM to avoid
external PROM SEU problem. The anti-fuse FPGA had strong resistance to SEU,
but the number of gates was relatively fewer and the speed was relatively slow for
such type.
SRAM-based FPGA was configured by loading status information into SRAM
to setup memory control, wiring, features, timing, I/O driver and etc. SRAM-based
FPGA provided users with maximum flexibility. When the FPGA was working, the
operation status of FPGA was setup by program stored in on-chip SRAM. During
operation, the SRAM on chip should be programmed in different program modes
according to different configuration modes. On power-up, the FPGA chip read the
configuration data from PROM into SRAM on chip. After the configuration was
completed, the FPGA was working. After the power was off, the FPGA recovered
to a white chip and the internal logic relationship disappears. Therefore, FPGAs
based on CMOS-SRAM technology could be repeatedly programmed and used,
and provide different functions by different program data in the same FPGA. From
analysis of design architecture, there might be SEU, SEFI, and SEL for SRAM type
FPGA.
For SRAM-based FPGA chip SEU faults, there were three ways to mitigate or
restore: reading configuration information for comparison, periodic or commandcontrolled reload, and triple-mode redundant design (TMR).
321
3. Anti-SEU Design of FPGA Chip
The development of microelectronics technology had created a good opportunity for
solving problems. FPGA was favored by aerospace designers for their high functional
density, small size, low power consumption, and semi-customized flexible configuration capabilities. Different types of FPGA chips had been widely used in Chinese
aerospace electronics products. The main reason was that user’s requirement for
spacecraft technology was improved, and onboard devices should have advantages
of high functionality, small size, light weight, and low power consumption, at the
same time, some functions could not be realized by general IC or computer software.
In addition, some new technologies and user requirements were difficult to be quickly
solidified, and technical solutions could only be determined through repeated trials
and technical coordination between users and contractors. So the project designer
could only use a powerful, flexible and convenient FPGA to develop the prototype.
Furthermore, once the project had been initiated, the FPGA application had become
a final decision. ASIC was certainly one of the important approaches of miniaturization, but its full custom development model that could not be flexibly modified was
difficult to adapt to the development requirement of new device.
There were currently two popular types of FPGA architecture: one was based on
SRAM and another was anti-fuse FPGA.
The anti-fuse type FPGA had the ability to resist Single Event Upset (SEU). By
permanent internal connection and program, the internal logic of chip could only
be burned once. After being programmed, the logic could not be changed and there
was no memory configured. Therefore, its anti-SEU performance was better than
that based on SRAM, and it was unnecessary to be configured with PROM to avoid
external PROM SEU problem. The anti-fuse FPGA had strong resistance to SEU,
but the number of gates was relatively fewer and the speed was relatively slow for
such type.
SRAM-based FPGA was configured by loading status information into SRAM
to setup memory control, wiring, features, timing, I/O driver and etc. SRAM-based
FPGA provided users with maximum flexibility. When the FPGA was working, the
operation status of FPGA was setup by program stored in on-chip SRAM. During
operation, the SRAM on chip should be programmed in different program modes
according to different configuration modes. On power-up, the FPGA chip read the
configuration data from PROM into SRAM on chip. After the configuration was
completed, the FPGA was working. After the power was off, the FPGA recovered
to a white chip and the internal logic relationship disappears. Therefore, FPGAs
based on CMOS-SRAM technology could be repeatedly programmed and used,
and provide different functions by different program data in the same FPGA. From
analysis of design architecture, there might be SEU, SEFI, and SEL for SRAM type
FPGA.
For SRAM-based FPGA chip SEU faults, there were three ways to mitigate or
restore: reading configuration information for comparison, periodic or commandcontrolled reload, and triple-mode redundant design (TMR).