80
P. Kumar et al.
Cu volume expansion, and more tensile away from the interface [20]. Conversely,
in addition to increasing the grain size, annealing lowers the compressive stresses in
the Cu.
Thermal cycling also leads to accumulation of hydrostatic stress in Cu TSV or
filler [27]. In addition, TSVs with high impurity levels appear to lead to high residual
stresses [15]. It has been reported that large tensile radial stresses exist at the Si–Cu
interface [25]; this may make these sites prone to failure in TSV assemblies. The
radial stress at the Cu-filler/Si interface generally increases with the length of the
TSV for a given diameter [25]. The TSV diameter also seems to affect the stress
state in the TSV assembly, although the dependence of the hydrostatic stress on TSV
diameter is not monotonic [36].
The stresses induced near the surface of Si next to the Cu-filled TSVs have an
adverse impact on the electrical performance of devices in the immediate neighborhood of the TSVs due to induced piezoresistivity, which results in degradation of
carrier mobility [37, 38]. This necessitates a keep-out zone (KOZ) in the Si, typically
a few micrometers in width, in the immediate vicinity of each TSV, where active
devices cannot be placed. The KOZ, which scales with the square of the TSV diameter, is also greater for high aspect-ratio TSVs, and places a significant overhead
on the area available in the chip for active devices, particularly with the increasing
density of TSVs in chips. Based on FEA of the stress-state in Si next to TSVs, it has
been inferred that Cu microstructures with smaller yield strengths reduce the KOZ
size, which increases with increasing yield strength until the via yields plastically,
and then remains stable [39].
FEA of TSVs in free-standing chips shows that after both heating and cooling,
maximum von Mises stress, and hence plastic deformation of the copper occurs near
the interface close to TSV-ends, which is a root cause of copper-pumping [40]. It is
further observed that the maximum principal stress (tensile) is in the radial direction at
the interface near the middle of the TSV, and in the circumferential dielectric layer
surrounding the TSV [41]. Evidence of dielectric cracking at the circumferential
Cu–SiO 2 –Si interface, as well as roughening (due to voiding) of the metal-line at
the top of the TSV has been noted after thermal cycling, as shown in Fig. 4.8 [42].
Fig. 4.8 TSV (a) prior to cycling, and after (b) 500 and (c) 2000 cycles between 30 and 150 °C,
showing development of dielectric cracks and top-line roughening [42]
P. Kumar et al.
Cu volume expansion, and more tensile away from the interface [20]. Conversely,
in addition to increasing the grain size, annealing lowers the compressive stresses in
the Cu.
Thermal cycling also leads to accumulation of hydrostatic stress in Cu TSV or
filler [27]. In addition, TSVs with high impurity levels appear to lead to high residual
stresses [15]. It has been reported that large tensile radial stresses exist at the Si–Cu
interface [25]; this may make these sites prone to failure in TSV assemblies. The
radial stress at the Cu-filler/Si interface generally increases with the length of the
TSV for a given diameter [25]. The TSV diameter also seems to affect the stress
state in the TSV assembly, although the dependence of the hydrostatic stress on TSV
diameter is not monotonic [36].
The stresses induced near the surface of Si next to the Cu-filled TSVs have an
adverse impact on the electrical performance of devices in the immediate neighborhood of the TSVs due to induced piezoresistivity, which results in degradation of
carrier mobility [37, 38]. This necessitates a keep-out zone (KOZ) in the Si, typically
a few micrometers in width, in the immediate vicinity of each TSV, where active
devices cannot be placed. The KOZ, which scales with the square of the TSV diameter, is also greater for high aspect-ratio TSVs, and places a significant overhead
on the area available in the chip for active devices, particularly with the increasing
density of TSVs in chips. Based on FEA of the stress-state in Si next to TSVs, it has
been inferred that Cu microstructures with smaller yield strengths reduce the KOZ
size, which increases with increasing yield strength until the via yields plastically,
and then remains stable [39].
FEA of TSVs in free-standing chips shows that after both heating and cooling,
maximum von Mises stress, and hence plastic deformation of the copper occurs near
the interface close to TSV-ends, which is a root cause of copper-pumping [40]. It is
further observed that the maximum principal stress (tensile) is in the radial direction at
the interface near the middle of the TSV, and in the circumferential dielectric layer
surrounding the TSV [41]. Evidence of dielectric cracking at the circumferential
Cu–SiO 2 –Si interface, as well as roughening (due to voiding) of the metal-line at
the top of the TSV has been noted after thermal cycling, as shown in Fig. 4.8 [42].
Fig. 4.8 TSV (a) prior to cycling, and after (b) 500 and (c) 2000 cycles between 30 and 150 °C,
showing development of dielectric cracks and top-line roughening [42]