3 Materials and Processing of TSV
61
Fig. 3.10 Micrographs showing cross-sectional view of Cu filled TSVs: (a) Time lapse images
at low magnification showing the fill front during bottom-up electroplating [52], and (b) at high
magnification TEM micrograph showing different material layers [53]. Cu electroplating in (a)
was performed at an applied potential of 0.600 V using electrolytic bath comprising of 1.0 mol/L
CuSO 4 , 0.5 mol/L H 2 SO 4 , 0.001 mol/L NaCl and 10 µ mol/L poloxamine (Tetronic 701) [52]
chloride ions to inhibit Cu deposition. An accelerator is adsorbed on the electrode
surface, where it gradually replaces the suppressor, thus allowing electroplating
of Cu to take place. Furthermore, coverage of an accelerator moves upwards, thus
enabling Cu filling to take place in a directional fashion from the bottom to the
top [50]. Levelers are used to improve filling performance, decrease the surface
roughness and prevent Cu deposition at the opening of the via [50]. Most of the
suppressors are polymers (e.g., polyethylene glycol (PEG), etc.) whereas common accelerators and levelers for Cu plating are 3-mercapto-1-propanesulfonate
(MPS), (3-sulfopropyl) disulfide (SPS), 3,3-thiobis (1-propanesulfonate) (TBPS),
etc., and Janus Green B (JGB), Diazine Black, Alcian Blue, etc., respectively [50].
As mentioned above, Cu is the most widely used filler for its very high electrical conductivity and compatibility with the backend structures, although in some
applications, W fillers are also used [51]. On the other hand, poly-silicon is compatible with the front-end structures (i.e., transistors) and its thermal expansion
coefficient is also similar to that of Si.
3.3.3 Planarization and Die-Thinning
As shown in Figs. 3.1b and 3.11a, after filling the metal in the Si via, there is
some excess metal or paste that is leftover on top of the wafer; this feature is called
overburden. There is a need for extra filling so that voids inside the filler can be
minimized. Also, due to the Cu-pumping phenomenon [54] (which will be discussed
in next chapter), Cu metal can protrude relative to the Si. In addition, if the metal is
not filled with proper overburden, the filler may shrink inside the Si via, leaving a
filler gap near its mouth. Therefore, there is a need for planarization of Si wafer on
61
Fig. 3.10 Micrographs showing cross-sectional view of Cu filled TSVs: (a) Time lapse images
at low magnification showing the fill front during bottom-up electroplating [52], and (b) at high
magnification TEM micrograph showing different material layers [53]. Cu electroplating in (a)
was performed at an applied potential of 0.600 V using electrolytic bath comprising of 1.0 mol/L
CuSO 4 , 0.5 mol/L H 2 SO 4 , 0.001 mol/L NaCl and 10 µ mol/L poloxamine (Tetronic 701) [52]
chloride ions to inhibit Cu deposition. An accelerator is adsorbed on the electrode
surface, where it gradually replaces the suppressor, thus allowing electroplating
of Cu to take place. Furthermore, coverage of an accelerator moves upwards, thus
enabling Cu filling to take place in a directional fashion from the bottom to the
top [50]. Levelers are used to improve filling performance, decrease the surface
roughness and prevent Cu deposition at the opening of the via [50]. Most of the
suppressors are polymers (e.g., polyethylene glycol (PEG), etc.) whereas common accelerators and levelers for Cu plating are 3-mercapto-1-propanesulfonate
(MPS), (3-sulfopropyl) disulfide (SPS), 3,3-thiobis (1-propanesulfonate) (TBPS),
etc., and Janus Green B (JGB), Diazine Black, Alcian Blue, etc., respectively [50].
As mentioned above, Cu is the most widely used filler for its very high electrical conductivity and compatibility with the backend structures, although in some
applications, W fillers are also used [51]. On the other hand, poly-silicon is compatible with the front-end structures (i.e., transistors) and its thermal expansion
coefficient is also similar to that of Si.
3.3.3 Planarization and Die-Thinning
As shown in Figs. 3.1b and 3.11a, after filling the metal in the Si via, there is
some excess metal or paste that is leftover on top of the wafer; this feature is called
overburden. There is a need for extra filling so that voids inside the filler can be
minimized. Also, due to the Cu-pumping phenomenon [54] (which will be discussed
in next chapter), Cu metal can protrude relative to the Si. In addition, if the metal is
not filled with proper overburden, the filler may shrink inside the Si via, leaving a
filler gap near its mouth. Therefore, there is a need for planarization of Si wafer on