17 Interconnect Quality and Reliability of 3D Packaging
531
BGA solder joint
Flip chip
solder joint (C4)
Microbumps
5-20μm
20μm
Fig. 17.1 Schematic diagram and optical image of a typical Chip-on-Wafer-on-Substrate (CoWoS)
architecture using 3-dimensional chip stacking with 2.5D silicon interposer (Yole Development
2013, Sakuma et al. 2015)
shown in Fig. 17.1. The interposer is between the vertically-stacked Si chips and the
packaging substrate to greatly relieve thermo-mechanical stress in the Si chips. One
of the prototypes of vertically stacked chips with Si interposer is shown in Fig. 17.2.
In a conventional flip chip solder joint, or Controlled-Collapse-Chip-Connection
(C4) joint, the IC chips with pre-deposited solders are flipped over so that top surface
of chip faces down and bonds with landing metal pads with a complex under bump
metallurgy (UBM). One of the major constituents of UBM is a thin layer of Cu pad.
In order to prevent the rapid Cu consumption by solder which may result in pancaketype electromigration (EM) void formation, typically a thin layer of Ni is deposited
on top of Cu to change the metallurgy of UBM and reduce the Cu consumption rate.
Hence only a small volume fraction of solder joint was converted to IMCs.
For the microbumps used in 3D IC technology, Thermal Compression Bonding
(TCB) is used to meet the requirement for fine pitch interconnect and high bonding
yield, especially in wafer-level packaging [4]. Copper pillar, instead of Cu thin film
UBM, is used to control the fine gap between chip-to-chip stacking. This results in
the utilization of low-volume and fine-cap Pb-free solder which is electroplated on
Cu pillar before TCB process to form microbumps. For a small size microbump, its
thickness is below 10 μm. Considering the large difference in terms of thickness and
Young’s modulus between Cu pillar (120 GPa) and Sn cap (50 GPa) of a microbump,
see Table 17.2, Cu pillar may induce large thermo-mechanical stress at joint interfaces compared to the conventional flip chip solder joints. Hence, microbump is
531
BGA solder joint
Flip chip
solder joint (C4)
Microbumps
5-20μm
20μm
Fig. 17.1 Schematic diagram and optical image of a typical Chip-on-Wafer-on-Substrate (CoWoS)
architecture using 3-dimensional chip stacking with 2.5D silicon interposer (Yole Development
2013, Sakuma et al. 2015)
shown in Fig. 17.1. The interposer is between the vertically-stacked Si chips and the
packaging substrate to greatly relieve thermo-mechanical stress in the Si chips. One
of the prototypes of vertically stacked chips with Si interposer is shown in Fig. 17.2.
In a conventional flip chip solder joint, or Controlled-Collapse-Chip-Connection
(C4) joint, the IC chips with pre-deposited solders are flipped over so that top surface
of chip faces down and bonds with landing metal pads with a complex under bump
metallurgy (UBM). One of the major constituents of UBM is a thin layer of Cu pad.
In order to prevent the rapid Cu consumption by solder which may result in pancaketype electromigration (EM) void formation, typically a thin layer of Ni is deposited
on top of Cu to change the metallurgy of UBM and reduce the Cu consumption rate.
Hence only a small volume fraction of solder joint was converted to IMCs.
For the microbumps used in 3D IC technology, Thermal Compression Bonding
(TCB) is used to meet the requirement for fine pitch interconnect and high bonding
yield, especially in wafer-level packaging [4]. Copper pillar, instead of Cu thin film
UBM, is used to control the fine gap between chip-to-chip stacking. This results in
the utilization of low-volume and fine-cap Pb-free solder which is electroplated on
Cu pillar before TCB process to form microbumps. For a small size microbump, its
thickness is below 10 μm. Considering the large difference in terms of thickness and
Young’s modulus between Cu pillar (120 GPa) and Sn cap (50 GPa) of a microbump,
see Table 17.2, Cu pillar may induce large thermo-mechanical stress at joint interfaces compared to the conventional flip chip solder joints. Hence, microbump is