378
S. G. Kandlikar and A. Ganguly
13.6.4 Emerging Wireless Interconnects for 3D ICs
with Liquid Cooling
The presence of active cooling layers in a 3D IC with microchannels of coolant liquid
imposes significant restrictions on where and how many TSVs and microchannels
can co-exist together. TSVs with Aspect Ratio (AR = Height/Diameter) greater
than 10 are very difficult to manufacture at high yield due to challenges related to
etching, sidewall passivation, and formation, insulation, and filling of Vias [14]. Codependency of the microchannels and electrical design makes the process even more
complex. Wider microchannels occupy significant portion of the floor area of the
3D IC severely restricting the freedom of placement and routing of TSV based links
in 3D multicore ICs. Moreover, increasing the microchannels height will eventually
increase the die thickness and consequently, the height of TSVs, which in turn will
increase the diameter of the TSVs to maintain a fixed AR. All these factors restrict
the area available to route TSVs across the cooling layers and make the co-existence
and co-design of TSVs and microchannels extremely challenging particularly where
thousands of TSVs are required for interconnections in large chips with die areas
higher than 100 mm
2 [14].
On the other hand, in recent years on-chip wireless interconnects in the millimeterwave frequency bands are demonstrated to be more energy-efficient compared to
conventional wireline interconnect fabrics [38–40]. Moreover, wireless interconnects
do not require physical layout of links and provide direct single-hop links between
transceivers distributed across the chips over a wireless Network-on-Chip (NoC).
NoC is an on-chip network which provides a scalable communication fabric among
multiple components of an IC [40]. Wireless NoCs (WiNoCs) enables low energy and
low latency communication among components or blocks in a multicore ICs. Based
on these recent studies, we evaluate the advantages and discuss the trade-offs of
realizing the vertical interconnects for data communication across the cooling layers
with on-chip wireless interconnects. This will reduce the number of TSV based links
across the microchannel layers as data transfer across the cooling layer will only
be achieved through wireless links. This will eliminate the need to place and route
signal TSVs across the cooling layers and significantly reduce the complexity of the
co-design of TSV based interconnects and microchannel based interlayer cooling.
Figure 13.1a shows the side-view of a 3D wireless NoC, and Fig. 13.1b shows the
top view of an active layer of 3D IC.
13.6.4.1 3D WiNoC Architecture
The cores in the 3D multicore system will be interconnected using a NoC fabric
through switches and links. In our proposed architecture, each core is connected
to a NoC switch. Switches within a single layer are connected in a mesh topology
with conventional copper wire based NoC links. To enable interlayer communication
S. G. Kandlikar and A. Ganguly
13.6.4 Emerging Wireless Interconnects for 3D ICs
with Liquid Cooling
The presence of active cooling layers in a 3D IC with microchannels of coolant liquid
imposes significant restrictions on where and how many TSVs and microchannels
can co-exist together. TSVs with Aspect Ratio (AR = Height/Diameter) greater
than 10 are very difficult to manufacture at high yield due to challenges related to
etching, sidewall passivation, and formation, insulation, and filling of Vias [14]. Codependency of the microchannels and electrical design makes the process even more
complex. Wider microchannels occupy significant portion of the floor area of the
3D IC severely restricting the freedom of placement and routing of TSV based links
in 3D multicore ICs. Moreover, increasing the microchannels height will eventually
increase the die thickness and consequently, the height of TSVs, which in turn will
increase the diameter of the TSVs to maintain a fixed AR. All these factors restrict
the area available to route TSVs across the cooling layers and make the co-existence
and co-design of TSVs and microchannels extremely challenging particularly where
thousands of TSVs are required for interconnections in large chips with die areas
higher than 100 mm
2 [14].
On the other hand, in recent years on-chip wireless interconnects in the millimeterwave frequency bands are demonstrated to be more energy-efficient compared to
conventional wireline interconnect fabrics [38–40]. Moreover, wireless interconnects
do not require physical layout of links and provide direct single-hop links between
transceivers distributed across the chips over a wireless Network-on-Chip (NoC).
NoC is an on-chip network which provides a scalable communication fabric among
multiple components of an IC [40]. Wireless NoCs (WiNoCs) enables low energy and
low latency communication among components or blocks in a multicore ICs. Based
on these recent studies, we evaluate the advantages and discuss the trade-offs of
realizing the vertical interconnects for data communication across the cooling layers
with on-chip wireless interconnects. This will reduce the number of TSV based links
across the microchannel layers as data transfer across the cooling layer will only
be achieved through wireless links. This will eliminate the need to place and route
signal TSVs across the cooling layers and significantly reduce the complexity of the
co-design of TSV based interconnects and microchannel based interlayer cooling.
Figure 13.1a shows the side-view of a 3D wireless NoC, and Fig. 13.1b shows the
top view of an active layer of 3D IC.
13.6.4.1 3D WiNoC Architecture
The cores in the 3D multicore system will be interconnected using a NoC fabric
through switches and links. In our proposed architecture, each core is connected
to a NoC switch. Switches within a single layer are connected in a mesh topology
with conventional copper wire based NoC links. To enable interlayer communication