10 Fundamentals of Bonding Technology and Process Materials …
325
References
1. S. Lee, Fundamental study of underfill void formation in flip chip assembly (2009)
2. S. Lee, R. Master, D.F. Baldwin, Assembly Yields Characterization of High I/O Density, Fine
Pitch Flip Chip in Package using No-Flow Underfill (Electronic Components and Technology
Conference, 2007), p. 35
3. S. Lee, R. Master, D.F. Baldwin, Assembly yields characterization and failure analysis of flip
chip in package using no-flow underfill. Int. Wafer Level Packag. Cong. 169–175 (2007)
4. S. Lee, R. Master, D.F. Baldwin, Void Formation Study of High I/O Density, Fine Pitch Flip Chip
in Package Using No-Flow Underfill (Surface Mount Technology Association International,
2007), pp. 525–530
5. S. Lee et al., Void formation study of flip chip in package using no-flow underfill. IEEE Trans.
Electron. Packag. Manuf. 31(4), 297–305 (2008)
6. S. Lee, et al., Assembly Yield Characterization and Void Formation Study on High I/O Density
and Fine Pitch Flip Chip in Package Using No-Flow Underfill (Surface Mount Technology
Association International, 2008), p. 673
7. S. Lee, M.J. Yim, D. Baldwin, Void formation mechanism of flip chip in package using no-flow
underfill. J. Electron. Packag. 131, 0310141–0310145 (2009)
8. S. Lee et al., Near void-free assembly development of flip chip using no-flow underfill. IEEE
Trans. Electron. Packag. Manuf. 32(2), 106–114 (2009)
9. S. Lee, D. Baldwin, Heterogeneous void nucleation study in flip chip assembly process using
no-flow underfill. ASME J. Electron. Packag. (In publishing) (2010)
10. S. Lee, H.-M. Zhou, D. Baldwin, A numerical study of void nucleation and growth in flip chip
assembly process. Model. Simul. Mater. Sci. Eng. 18(6), 065005–065025 (2010)
11. A. Eitan, K.Y. Hung, Thermo-Compression Bonding for fine-pitch copper-pillar flip-chip
interconnect—tool features as enablers of unique technology. in 2015 IEEE 65 th Electronic
Components and Technology Conference (ECTC) (2015)
12. J.H. Lau, The future of interposer for semiconductor IC packaging. Chip Scale Rev. 18(1),
32–36 (2014)
13. Package Analysis of the SK-Hynix High Bandwidth Memory (HBM) (2015)
14. W.-S. Kwon, et al., Enabling a manufacturable 3D technologies and ecosystem using
28 nm FPGA with stack silicon interconnect technology. in International Symposium on
Microelectronics (International Microelectronics Assembly and Packaging Society, 2013)
15. K. Ichikawa, Key Technology Challenges in Computing Package and Assembly (Assembly
Technology Development Japan, Intel Corporation, 2014)
16. S. Lau, Thermo-compression bonding for fine-pitch copper pillar flip chip interconnect, in
SEMICON Advanced Packaging Symposium (ASMPT, Taiwan, 2014)
17. Z. Li, et al. Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon
assembly yield, reliability and intermetallic compound characteristics. in 2010 Proceedings
60th Electronic Components and Technology Conference (ECTC) (IEEE, 2010)
18. C.G. Woychik, et al., New approaches to develop a scalable 3D IC assembly method. J. Microel.
Electron. Packag. (2015)
19. D.S. Patterson, 2.5 D/3D Packaging enablement through copper pillar technology. Chip Scale
Rev. 16(3), 20–26 (2012)
20. C. Wong, S.H. Shi, G. Jefferson, High performance no-flow underfills for low-cost flip-chip
applications: material characterization. Compon. Packag. Manuf. Technol. Part A IEEE Trans.
21(3), 450–458 (1998)
21. C.P. Wong, et al., Characterization of a no-flow underfill encapsulant during the solder reflow
process. in Electronic Components and Technology Conference, 1998. 48th IEEE (1998)
22. C.P. Wong, S.H. Shi, G. Jefferson, High performance no-flow underfills for low-cost flip-chip
applications: materials characterization. IEEE Trans. Componen. Hybrids Manuf. Technol. 21,
450–458 (1998)
325
References
1. S. Lee, Fundamental study of underfill void formation in flip chip assembly (2009)
2. S. Lee, R. Master, D.F. Baldwin, Assembly Yields Characterization of High I/O Density, Fine
Pitch Flip Chip in Package using No-Flow Underfill (Electronic Components and Technology
Conference, 2007), p. 35
3. S. Lee, R. Master, D.F. Baldwin, Assembly yields characterization and failure analysis of flip
chip in package using no-flow underfill. Int. Wafer Level Packag. Cong. 169–175 (2007)
4. S. Lee, R. Master, D.F. Baldwin, Void Formation Study of High I/O Density, Fine Pitch Flip Chip
in Package Using No-Flow Underfill (Surface Mount Technology Association International,
2007), pp. 525–530
5. S. Lee et al., Void formation study of flip chip in package using no-flow underfill. IEEE Trans.
Electron. Packag. Manuf. 31(4), 297–305 (2008)
6. S. Lee, et al., Assembly Yield Characterization and Void Formation Study on High I/O Density
and Fine Pitch Flip Chip in Package Using No-Flow Underfill (Surface Mount Technology
Association International, 2008), p. 673
7. S. Lee, M.J. Yim, D. Baldwin, Void formation mechanism of flip chip in package using no-flow
underfill. J. Electron. Packag. 131, 0310141–0310145 (2009)
8. S. Lee et al., Near void-free assembly development of flip chip using no-flow underfill. IEEE
Trans. Electron. Packag. Manuf. 32(2), 106–114 (2009)
9. S. Lee, D. Baldwin, Heterogeneous void nucleation study in flip chip assembly process using
no-flow underfill. ASME J. Electron. Packag. (In publishing) (2010)
10. S. Lee, H.-M. Zhou, D. Baldwin, A numerical study of void nucleation and growth in flip chip
assembly process. Model. Simul. Mater. Sci. Eng. 18(6), 065005–065025 (2010)
11. A. Eitan, K.Y. Hung, Thermo-Compression Bonding for fine-pitch copper-pillar flip-chip
interconnect—tool features as enablers of unique technology. in 2015 IEEE 65 th Electronic
Components and Technology Conference (ECTC) (2015)
12. J.H. Lau, The future of interposer for semiconductor IC packaging. Chip Scale Rev. 18(1),
32–36 (2014)
13. Package Analysis of the SK-Hynix High Bandwidth Memory (HBM) (2015)
14. W.-S. Kwon, et al., Enabling a manufacturable 3D technologies and ecosystem using
28 nm FPGA with stack silicon interconnect technology. in International Symposium on
Microelectronics (International Microelectronics Assembly and Packaging Society, 2013)
15. K. Ichikawa, Key Technology Challenges in Computing Package and Assembly (Assembly
Technology Development Japan, Intel Corporation, 2014)
16. S. Lau, Thermo-compression bonding for fine-pitch copper pillar flip chip interconnect, in
SEMICON Advanced Packaging Symposium (ASMPT, Taiwan, 2014)
17. Z. Li, et al. Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon
assembly yield, reliability and intermetallic compound characteristics. in 2010 Proceedings
60th Electronic Components and Technology Conference (ECTC) (IEEE, 2010)
18. C.G. Woychik, et al., New approaches to develop a scalable 3D IC assembly method. J. Microel.
Electron. Packag. (2015)
19. D.S. Patterson, 2.5 D/3D Packaging enablement through copper pillar technology. Chip Scale
Rev. 16(3), 20–26 (2012)
20. C. Wong, S.H. Shi, G. Jefferson, High performance no-flow underfills for low-cost flip-chip
applications: material characterization. Compon. Packag. Manuf. Technol. Part A IEEE Trans.
21(3), 450–458 (1998)
21. C.P. Wong, et al., Characterization of a no-flow underfill encapsulant during the solder reflow
process. in Electronic Components and Technology Conference, 1998. 48th IEEE (1998)
22. C.P. Wong, S.H. Shi, G. Jefferson, High performance no-flow underfills for low-cost flip-chip
applications: materials characterization. IEEE Trans. Componen. Hybrids Manuf. Technol. 21,
450–458 (1998)