1 Introduction to 3D Microelectronic Packaging
15
building up efficient 3D packaging FI-FA flow and performing in-depth root cause
studies, along with case study demonstration.
1.5 Summary
3D packaging has provided a new dimension for semiconductor industry to maintain
Moore’s law with much lower cost, and has been adopted as an effective approach to
provide portable microelectronics with better performance, smaller power consumption, and less cost. There has been numerous novel technological innovations invented
for the development of advanced 3D packaging in the recent years. However, due to
the much smaller and denser interconnects, complicated assembly process, unique
TSV and micro-bump TCB process, and the extended application in high reliability
products, there are tremendous challenges in highly integrated 3D packaging.
Chapters in this book are written by experts from both academia and semiconductor industry. Chapter 2 provides an insightful overview of 3D packaging architecture and assembly process design. Chapters 3–7 focus on the fundamentals of TSV
processing, reliability, and mechanical properties. Chapters 8–10 discuss the fundamentals of thermal compression bonding of micro bumps, process materials, direct
Cu to Cu bonding, and other alternative interconnects in 3D packaging. Chapters 11
and 12 provide fundamentals of solder alloys and electro migration in interconnects
of 3D packages. Chapter 13 presents a thorough review of thermal management in 3D
packaging. Chapter 14 displays in great details the fundamentals of substrate materials and manufacture process. Chapter 15 covers the thermal mechanical and moisture modeling in 3D packaging. Chapter 16–18 illustrate a comprehensive overview
of quality, reliability, fault isolation, and failure analysis of advanced 3D packages. Readers could obtain all-around knowledge about 3D packaging, including the
fundamentals, developing areas, technique gaps, and guidelines for future research
and development.
Acknowledgements The editors would like to thank John Elmer from Lawrence Livermore
National Laboratory for his critical review of this chapter.
References
1. I. Szendiuch, Radioengineering 20(1), 214 (2011)
2. S.F. Al-sarawi, D. Abbott, P.D. Franzon, IEEE Trans. Compon. Pack. Manufact. Technol. Part
B 21(1), 2 (1998)
3. J.Q. Lu, Proc. IEEE 97(1), 18 (2009)
4. J.H. Lau, Chip Scale Rev. 18(1), 32 (2014)
5. L. Li, P. Chia, P. Ton, M. Nagar, S. Patil, J. Xue, J. DeLaCruz, M. Voicu, J. Hellings, B. Isaacson,
M. Coor, R. Havens, in Conference Proceedings from the 66th Electronic Components and
Technology Conference (ECTC) (2016), p. 1445
15
building up efficient 3D packaging FI-FA flow and performing in-depth root cause
studies, along with case study demonstration.
1.5 Summary
3D packaging has provided a new dimension for semiconductor industry to maintain
Moore’s law with much lower cost, and has been adopted as an effective approach to
provide portable microelectronics with better performance, smaller power consumption, and less cost. There has been numerous novel technological innovations invented
for the development of advanced 3D packaging in the recent years. However, due to
the much smaller and denser interconnects, complicated assembly process, unique
TSV and micro-bump TCB process, and the extended application in high reliability
products, there are tremendous challenges in highly integrated 3D packaging.
Chapters in this book are written by experts from both academia and semiconductor industry. Chapter 2 provides an insightful overview of 3D packaging architecture and assembly process design. Chapters 3–7 focus on the fundamentals of TSV
processing, reliability, and mechanical properties. Chapters 8–10 discuss the fundamentals of thermal compression bonding of micro bumps, process materials, direct
Cu to Cu bonding, and other alternative interconnects in 3D packaging. Chapters 11
and 12 provide fundamentals of solder alloys and electro migration in interconnects
of 3D packages. Chapter 13 presents a thorough review of thermal management in 3D
packaging. Chapter 14 displays in great details the fundamentals of substrate materials and manufacture process. Chapter 15 covers the thermal mechanical and moisture modeling in 3D packaging. Chapter 16–18 illustrate a comprehensive overview
of quality, reliability, fault isolation, and failure analysis of advanced 3D packages. Readers could obtain all-around knowledge about 3D packaging, including the
fundamentals, developing areas, technique gaps, and guidelines for future research
and development.
Acknowledgements The editors would like to thank John Elmer from Lawrence Livermore
National Laboratory for his critical review of this chapter.
References
1. I. Szendiuch, Radioengineering 20(1), 214 (2011)
2. S.F. Al-sarawi, D. Abbott, P.D. Franzon, IEEE Trans. Compon. Pack. Manufact. Technol. Part
B 21(1), 2 (1998)
3. J.Q. Lu, Proc. IEEE 97(1), 18 (2009)
4. J.H. Lau, Chip Scale Rev. 18(1), 32 (2014)
5. L. Li, P. Chia, P. Ton, M. Nagar, S. Patil, J. Xue, J. DeLaCruz, M. Voicu, J. Hellings, B. Isaacson,
M. Coor, R. Havens, in Conference Proceedings from the 66th Electronic Components and
Technology Conference (ECTC) (2016), p. 1445