1 Introduction to 3D Microelectronic Packaging
13
1.4.2 Thermal Management, Package Design, and Modeling
Challenges
The 3D integration of heat generation components in close vicinity increases the
heat flux density as well as complexity of coolant routing, thus leads to big challenges to the thermal management of 3D packaging [2, 3]. Chapter 13 presents the
fundamentals of heat transfer along with advanced guidelines helpful to address the
issue.
Due to the increased system complexity, designing 3D packages could be very
challenging, but could be addressed by designing and developing design software [2].
In addition to increased system complexity, 3D packaging involves multi-levels of
solder joints, underfill, and molding compounds. Thermal stress due to the mismatch
in coefficients of thermal expansion (CTE) and hygroscopic stress caused by excessive moisture absorption are often combined together, which complicates the stress
modeling in 3D packaging [22, 23]. For interconnects with a couple of micrometer
in diameter, like TSVs, it is found that microstructure, anisotropy of material properties, recrystallization, and time-dependent phase morphological evolution need to
be considered during stress modeling [24]. Chapters 4–6 and 16 provide thorough
discussions on the modeling of thermal mechanical and moisture stresses in 3D
packaging.
1.4.3 Material and Substrate Challenges
3D packages typically have smaller interconnect size, tighter bump pitch, and reduced
chip gap, which brings challenges to underfill, chip attachment, and deflux process.
Additionally, the TCB process widely used in the chip attachment of 3D packages
is very different from the conventional mass reflow process, as the whole bonding
cycle completes in a few seconds rather than over 10 min [19]. Major modification
of traditional underfill and flux material is essential to prevent underfill process,
flux residue, and interconnect integrity induced yield loss, such as underfill voids,
delamination because of flux residue, solder bump bridging or non-wets. Chapter 10
reviews the material challenges and provides guidelines for epoxy and flux material
selection.
To enable the highly integrated 3D packaging, both substrate and PCB need to
fulfill the much higher signal and power density requirements. Smaller substrate vias,
through holes (TH), and traces, along with much tighter pitches are desired. Furthermore embedded components, including both Si chip and packages, integrating into
substrates or PCB is one of the approaches to achieve the product miniaturization with
higher performance and lower power consumption goal. These result in significant
challenges in substrate warpage control and flawless fabrication process to enable
much finer interconnect size and pitch. Chapter 14 reviews the substrate material and
13
1.4.2 Thermal Management, Package Design, and Modeling
Challenges
The 3D integration of heat generation components in close vicinity increases the
heat flux density as well as complexity of coolant routing, thus leads to big challenges to the thermal management of 3D packaging [2, 3]. Chapter 13 presents the
fundamentals of heat transfer along with advanced guidelines helpful to address the
issue.
Due to the increased system complexity, designing 3D packages could be very
challenging, but could be addressed by designing and developing design software [2].
In addition to increased system complexity, 3D packaging involves multi-levels of
solder joints, underfill, and molding compounds. Thermal stress due to the mismatch
in coefficients of thermal expansion (CTE) and hygroscopic stress caused by excessive moisture absorption are often combined together, which complicates the stress
modeling in 3D packaging [22, 23]. For interconnects with a couple of micrometer
in diameter, like TSVs, it is found that microstructure, anisotropy of material properties, recrystallization, and time-dependent phase morphological evolution need to
be considered during stress modeling [24]. Chapters 4–6 and 16 provide thorough
discussions on the modeling of thermal mechanical and moisture stresses in 3D
packaging.
1.4.3 Material and Substrate Challenges
3D packages typically have smaller interconnect size, tighter bump pitch, and reduced
chip gap, which brings challenges to underfill, chip attachment, and deflux process.
Additionally, the TCB process widely used in the chip attachment of 3D packages
is very different from the conventional mass reflow process, as the whole bonding
cycle completes in a few seconds rather than over 10 min [19]. Major modification
of traditional underfill and flux material is essential to prevent underfill process,
flux residue, and interconnect integrity induced yield loss, such as underfill voids,
delamination because of flux residue, solder bump bridging or non-wets. Chapter 10
reviews the material challenges and provides guidelines for epoxy and flux material
selection.
To enable the highly integrated 3D packaging, both substrate and PCB need to
fulfill the much higher signal and power density requirements. Smaller substrate vias,
through holes (TH), and traces, along with much tighter pitches are desired. Furthermore embedded components, including both Si chip and packages, integrating into
substrates or PCB is one of the approaches to achieve the product miniaturization with
higher performance and lower power consumption goal. These result in significant
challenges in substrate warpage control and flawless fabrication process to enable
much finer interconnect size and pitch. Chapter 14 reviews the substrate material and