226
T. Suga et al.
meeting requirements for various interconnect domains (e.g. sensors, memory-onlogic and higher-IO density logic-on-logic) and applications (automotive, mobile,
client, server). Adoption of new technology is not solely a technical challenge but also
a business challenge which involves new equipment investments and timely introduction to enable adequate product volumes for high volume manufacturing (HVM).
Eliminating solders and solder intermetallic compounds (IMC’s) seems promising,
however Cu-only interconnects are also prone to electromigration. Cu alloying and
doping evolving from SAB methods, new protective layers and novel processing
[83] and Cobalt demonstrations have been researched [84] and in special cases also
deployed [85]. In the long term, advanced materials (e.g. 2D/nanomaterials) may be
introduced as auxiliary materials for Cu–Cu enabling or even as key interconnect
materials with potential to replace Cu altogether [86]. As Prof. Feynman once said:
“There is plenty of room at the bottom.”
Acknowledgements The editors would like to thank Hualiang Shi and Debendra Mallik of Intel
Corporation for their critical review of this Chapter.
References
1. A. Fan, A. Rahman, R. Reif, Copper wafer bonding. Electrochem. Solid-State Lett. 2, 534–536
(1999). https://doi.org/10.1149/1.1390894
2. A. Shigetou, N. Hosoda, T. Itoh, T. Suga, Room-temperature direct bonding of CMP-Cu film
for bumpless interconnection, in 2001 51st Electron Electronic Components and Technology
Conference (Orlando, FL, 2001), pp 755–760
3. P.R. Morrow, C.-M. Park, S. Ramanathan, M.J. Kobrinsky, M. Harmes, Three-dimensional
wafer stacking via Cu–Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology.
IEEE Electron Device Lett. 27, 335–337 (2006). https://doi.org/10.1109/LED.2006.873424
4. A. Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, T. Suga, Bumpless interconnect
through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method. IEEE
Trans. Adv. Packag. 29, 218–226 (2006). https://doi.org/10.1109/TADVP.2006.873138
5. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens,
S. Stoukatch, D.S. Tezcan, Z. Tokei, J. Vaes, 3D integration by Cu–Cu thermo-compression
bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias, in 2006
International Electron Devices Meeting (IEEE, 2006), pp. 1–4
6. Tezzaron Company History. http://www.tezzaron.com/about-us/company-history. Accessed 18
Jun 2016
7. G.W. Deptuch, M. Demarteau, J.R. Hoff, R. Lipton, A. Shenai, M. Trimpl, R. Yarema, T.
Zimmerman, Vertically integrated circuits at Fermilab. IEEE Trans. Nucl. Sci. 57, 2178–2186
(2010). https://doi.org/10.1109/TNS.2010.2049659
8. R. Yarema, G. Deptuch, J. Hoff, F. Khalid, R. Lipton, A. Shenai, M. Trimpl, T. Zimmerman,
Vertically integrated circuit development at Fermilab for detectors. J. Instrum. 8, C01052
(2013). https://doi.org/10.1088/1748-0221/8/01/C01052
9. Chipworks, Samsung Galaxy S7 Edge Teardown Report, 2016
10. M. Higashiwaki, K. Sasaki, T. Kamimura, M.H. Wong, D. Krishnamurthy, A. Kuramata, T.
Masui, S. Yamakoshi, Depletion-mode Ga2O3 metal-oxide-semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics.
Appl. Phys. Lett. 103, 123511 (2013). https://doi.org/10.1063/1.4821858
T. Suga et al.
meeting requirements for various interconnect domains (e.g. sensors, memory-onlogic and higher-IO density logic-on-logic) and applications (automotive, mobile,
client, server). Adoption of new technology is not solely a technical challenge but also
a business challenge which involves new equipment investments and timely introduction to enable adequate product volumes for high volume manufacturing (HVM).
Eliminating solders and solder intermetallic compounds (IMC’s) seems promising,
however Cu-only interconnects are also prone to electromigration. Cu alloying and
doping evolving from SAB methods, new protective layers and novel processing
[83] and Cobalt demonstrations have been researched [84] and in special cases also
deployed [85]. In the long term, advanced materials (e.g. 2D/nanomaterials) may be
introduced as auxiliary materials for Cu–Cu enabling or even as key interconnect
materials with potential to replace Cu altogether [86]. As Prof. Feynman once said:
“There is plenty of room at the bottom.”
Acknowledgements The editors would like to thank Hualiang Shi and Debendra Mallik of Intel
Corporation for their critical review of this Chapter.
References
1. A. Fan, A. Rahman, R. Reif, Copper wafer bonding. Electrochem. Solid-State Lett. 2, 534–536
(1999). https://doi.org/10.1149/1.1390894
2. A. Shigetou, N. Hosoda, T. Itoh, T. Suga, Room-temperature direct bonding of CMP-Cu film
for bumpless interconnection, in 2001 51st Electron Electronic Components and Technology
Conference (Orlando, FL, 2001), pp 755–760
3. P.R. Morrow, C.-M. Park, S. Ramanathan, M.J. Kobrinsky, M. Harmes, Three-dimensional
wafer stacking via Cu–Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology.
IEEE Electron Device Lett. 27, 335–337 (2006). https://doi.org/10.1109/LED.2006.873424
4. A. Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, T. Suga, Bumpless interconnect
through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method. IEEE
Trans. Adv. Packag. 29, 218–226 (2006). https://doi.org/10.1109/TADVP.2006.873138
5. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens,
S. Stoukatch, D.S. Tezcan, Z. Tokei, J. Vaes, 3D integration by Cu–Cu thermo-compression
bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias, in 2006
International Electron Devices Meeting (IEEE, 2006), pp. 1–4
6. Tezzaron Company History. http://www.tezzaron.com/about-us/company-history. Accessed 18
Jun 2016
7. G.W. Deptuch, M. Demarteau, J.R. Hoff, R. Lipton, A. Shenai, M. Trimpl, R. Yarema, T.
Zimmerman, Vertically integrated circuits at Fermilab. IEEE Trans. Nucl. Sci. 57, 2178–2186
(2010). https://doi.org/10.1109/TNS.2010.2049659
8. R. Yarema, G. Deptuch, J. Hoff, F. Khalid, R. Lipton, A. Shenai, M. Trimpl, T. Zimmerman,
Vertically integrated circuit development at Fermilab for detectors. J. Instrum. 8, C01052
(2013). https://doi.org/10.1088/1748-0221/8/01/C01052
9. Chipworks, Samsung Galaxy S7 Edge Teardown Report, 2016
10. M. Higashiwaki, K. Sasaki, T. Kamimura, M.H. Wong, D. Krishnamurthy, A. Kuramata, T.
Masui, S. Yamakoshi, Depletion-mode Ga2O3 metal-oxide-semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics.
Appl. Phys. Lett. 103, 123511 (2013). https://doi.org/10.1063/1.4821858