Chapter 1
Introduction to 3D Microelectronic
Packaging
Yan Li and Deepak Goyal
1.1 Introduction
Microelectronic packaging is the bridge between the Integrated Circuit (IC) and
the electronic system, which incorporates all technologies used between them [1].
Advanced 3D microelectronic packaging technology is the industry trend to meet
portable electronics demand of ultra-thin, ultra-light, high performance with low
power consumption. It also opens up a new dimension for the semiconductor industry
to maintain Moore’s law with a much lower cost [1–3].
A wide variety of real products assembled by the advanced 3D packaging technology have been unveiled in the recent years. For example, the Apple A7 inside
the iPhone 5S, introduced in September 2013, is a 3D package with Package on
Package (POP) configuration [4]. As displayed in Fig. 1.1, the wire bond Elpida
(now Micron) memory (low power double data rate type-3 (LPDDR3) mobile random
access memory (RAM)) package is stacked on top of the Apple A7 flip chip package
to achieve better performance with smaller form factor. In early 2014, SK Hynix
announced its high bandwidth memory (HBM) products having higher bandwidth,
less power consumption, and substantially small form factor, achieved by stacking up
to eight DRAM dice interconnected through Through Silicon Vias (TSV) and micro
bumps [5]. In July of 2015, AMD introduced the AMD Radeon™ Fury graphics
cards, the first Graphic Processing Unit (GPU) to implement HBM by TSVs and
micro bumps [6]. Figure 1.2 shows a top down and schematic cross sectional view
of the advanced 3D package. The big GPU die is integrated into the Si interposer
Y. Li (B) · D. Goyal
Intel Corporation, Chandler, AZ, USA
e-mail: yan.a.li@intel.com
D. Goyal
e-mail: Deepak.goyal@intel.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_1
1
Introduction to 3D Microelectronic
Packaging
Yan Li and Deepak Goyal
1.1 Introduction
Microelectronic packaging is the bridge between the Integrated Circuit (IC) and
the electronic system, which incorporates all technologies used between them [1].
Advanced 3D microelectronic packaging technology is the industry trend to meet
portable electronics demand of ultra-thin, ultra-light, high performance with low
power consumption. It also opens up a new dimension for the semiconductor industry
to maintain Moore’s law with a much lower cost [1–3].
A wide variety of real products assembled by the advanced 3D packaging technology have been unveiled in the recent years. For example, the Apple A7 inside
the iPhone 5S, introduced in September 2013, is a 3D package with Package on
Package (POP) configuration [4]. As displayed in Fig. 1.1, the wire bond Elpida
(now Micron) memory (low power double data rate type-3 (LPDDR3) mobile random
access memory (RAM)) package is stacked on top of the Apple A7 flip chip package
to achieve better performance with smaller form factor. In early 2014, SK Hynix
announced its high bandwidth memory (HBM) products having higher bandwidth,
less power consumption, and substantially small form factor, achieved by stacking up
to eight DRAM dice interconnected through Through Silicon Vias (TSV) and micro
bumps [5]. In July of 2015, AMD introduced the AMD Radeon™ Fury graphics
cards, the first Graphic Processing Unit (GPU) to implement HBM by TSVs and
micro bumps [6]. Figure 1.2 shows a top down and schematic cross sectional view
of the advanced 3D package. The big GPU die is integrated into the Si interposer
Y. Li (B) · D. Goyal
Intel Corporation, Chandler, AZ, USA
e-mail: yan.a.li@intel.com
D. Goyal
e-mail: Deepak.goyal@intel.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_1
1