7 Fundamentals and Failures in Die Preparation for 3D Packaging
163
seed layer deposition by PVD and copper electroplating. The plating chemistry and
process need to be optimized to reduce the risk of TSV copper void and extrusion
[31].
Compared with Via Last, the TSV copper in Via Middle can go through the high
temperature BEOL copper annealing process, which reduces the risk of TSV copper
extrusion. Some groups also developed electroless barrier layer deposition process to
save cost [32]. Once TSV copper deposition process is done, Chemical Mechanical
Polish (CMP) process is employed to remove the TSV copper overburden. Similar
as indentation effect, low-k dielectric delamination or crack underneath TSV might
occur during the CMP process. After CMP process, similar as traditional BEOL
process and C4 bumping process, redistribution layer and micro bump can be formed.
Then, the thinned device wafer can be debonded from carrier wafer by thermal slideoff, mechanical release, and laser release [10–13, 33, 34], which is illustrated in
Fig. 7.5 and discussed in detail in Sect. 5.4. In thermal slide-off, heat and mechanical
force are used to slide off device wafer relative to carrier wafer. In mechanical
release, the separation is initiated from wafer edge and the carrier wafer is lifted off
in a perpendicular direction, while wafer is mounted on dicing tape. In laser release,
laser penetrates the optically transparent wafer and ablate or react with the release
layer before carrier wafer lift-off.
Wafer singulation is one of the key assembly steps. In order to meet throughput,
yield, and reliability targets, efficient process is required. Generation after generation, the requirement becomes more challenging due to the enhancement in package
design, such as package form factor reduction and complex low-k inter-layer dielectric (ILD)materials. In the case of 3D interconnect, the material properties, ILD
stack-up and metal density in the wafer street region makes the singulation process
extremely challenging. Typical process flows for wafer singulation are shown in
Fig. 7.2. As indicated in Fig. 7.2a, post wafer debond process, the thin device wafer
is mounted at the top of dicing tape. The wafer is then singulated using a diamond
saw blade. The blade cut through the wafer street center region to separate active dies.
Figure 7.6 shows typical defects induced by mechanical saw dicing process [35]. The
optimization of saw blade type and process condition are crucial in reducing these
defects. Last, die ejector is employed to pick the chips from dicing tape and place
them into tape and reel or direct chip attach. The ejector pin or blade design and
configuration, and process conditions need to be optimized to reduce the die chipping and crack risks. The sensitivity of these factors are critical especially for thin die
pick and place as can lead to severe die crack. Figure 7.2b has extra wafer coat and
laser scribe processes before diamond saw cutting process. Further scaling of technology node and new low-k ILD materials introduced, singulation with saw blade
becomes challenging. Due to the weak mechanical property, these low-k ILD materials have crack and delamination risks during the mechanical saw dicing process. In
this scenario laser scribe is applied to remove the low-k ILD and ETEST structures
in the street area such that the saw blade interact with ILD layer near active die
during mechanical saw dicing. During laser scribe process, Si and ILD debris might
be generated and re-deposited on the wafer surface, which can induce non-wet or
non-contact open yield loss during chip attach process. This also may lead to epoxy
163
seed layer deposition by PVD and copper electroplating. The plating chemistry and
process need to be optimized to reduce the risk of TSV copper void and extrusion
[31].
Compared with Via Last, the TSV copper in Via Middle can go through the high
temperature BEOL copper annealing process, which reduces the risk of TSV copper
extrusion. Some groups also developed electroless barrier layer deposition process to
save cost [32]. Once TSV copper deposition process is done, Chemical Mechanical
Polish (CMP) process is employed to remove the TSV copper overburden. Similar
as indentation effect, low-k dielectric delamination or crack underneath TSV might
occur during the CMP process. After CMP process, similar as traditional BEOL
process and C4 bumping process, redistribution layer and micro bump can be formed.
Then, the thinned device wafer can be debonded from carrier wafer by thermal slideoff, mechanical release, and laser release [10–13, 33, 34], which is illustrated in
Fig. 7.5 and discussed in detail in Sect. 5.4. In thermal slide-off, heat and mechanical
force are used to slide off device wafer relative to carrier wafer. In mechanical
release, the separation is initiated from wafer edge and the carrier wafer is lifted off
in a perpendicular direction, while wafer is mounted on dicing tape. In laser release,
laser penetrates the optically transparent wafer and ablate or react with the release
layer before carrier wafer lift-off.
Wafer singulation is one of the key assembly steps. In order to meet throughput,
yield, and reliability targets, efficient process is required. Generation after generation, the requirement becomes more challenging due to the enhancement in package
design, such as package form factor reduction and complex low-k inter-layer dielectric (ILD)materials. In the case of 3D interconnect, the material properties, ILD
stack-up and metal density in the wafer street region makes the singulation process
extremely challenging. Typical process flows for wafer singulation are shown in
Fig. 7.2. As indicated in Fig. 7.2a, post wafer debond process, the thin device wafer
is mounted at the top of dicing tape. The wafer is then singulated using a diamond
saw blade. The blade cut through the wafer street center region to separate active dies.
Figure 7.6 shows typical defects induced by mechanical saw dicing process [35]. The
optimization of saw blade type and process condition are crucial in reducing these
defects. Last, die ejector is employed to pick the chips from dicing tape and place
them into tape and reel or direct chip attach. The ejector pin or blade design and
configuration, and process conditions need to be optimized to reduce the die chipping and crack risks. The sensitivity of these factors are critical especially for thin die
pick and place as can lead to severe die crack. Figure 7.2b has extra wafer coat and
laser scribe processes before diamond saw cutting process. Further scaling of technology node and new low-k ILD materials introduced, singulation with saw blade
becomes challenging. Due to the weak mechanical property, these low-k ILD materials have crack and delamination risks during the mechanical saw dicing process. In
this scenario laser scribe is applied to remove the low-k ILD and ETEST structures
in the street area such that the saw blade interact with ILD layer near active die
during mechanical saw dicing. During laser scribe process, Si and ILD debris might
be generated and re-deposited on the wafer surface, which can induce non-wet or
non-contact open yield loss during chip attach process. This also may lead to epoxy