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H. Ma et al.
process, along with post debond cleaning, are investigated. Based on the simple
viscosity definition and wafer geometry, a close-form analytical solution is proposed
for the thermal slide-off wafer debonding process, which can be used for process
control and throughput optimization. The next two processes discussed are laser
scribe and saw dicing, which impact die chipping and delamination. A closed-form
solution of chipping induced by saw dicing is also investigated. In addition, the challenges and solution options for die eject and attach are discussed. Last but not least,
key factors affecting epoxy flow time are studied, and options to reduce the epoxy
keep-out-zone (KOZ) are proposed.
7.2 Brief Overview of TSV Wafer Fabrication Processes
Different TSV wafer fabrication approaches have been reported [6, 7], including Via
First, Via Middle, and Via Last. In Via First, TSV is fabricated before Front-End-ofLine process. In Via Middle, TSV is fabricated after Front-End-of-Line process and
before Back-End-of-Line process. In Via Last, TSV is fabricated after Back-End-ofLine process. Please refer to Chap. 3 for details. The advantages and disadvantages
of different TSV fabrication approaches have been reviewed by several groups and
are beyond the scope of this chapter. In the following, Via Last approach is used
as case study to highlight some key process issues and failure modes. The typical
temporary bonding process flow is shown in Fig. 7.1, and post debond, the typical
singulation process flow is shown in Fig. 7.2.
Post C4 bumping process, device wafer gets edge trimming first to avoid yield loss
due to defects such as wafer edge crack, chipping, and delamination, especially in the
region with adhesive coverage issue [8]. Then, as indicated in Fig. 7.3, device wafer
is attached to carrier wafer by using temporary bonding adhesive [1, 2, 9]. Carrier
wafer can be silicon wafer or optically transparent wafer such as glass, sapphire, and
quartz. Temporary adhesive can be thermal setting polymers, such as epoxies, polyimides, and photoresists, or thermal plastic polymers, such as polydimethylsiloxane
(PDMS), polymethylmethacrylate (PMMA), and polyetherketone (PEEK) [1]. The
material properties of bonding adhesive need to be optimized to improve process
yield and bonding quality [10–13]. The bonding adhesive should have good thermal
resistance and chemical resistance to withstand acid, alkalis, and solvents used at
elevated temperature during different downstream processes, have good adhesion
with both device wafer and carrier wafer to survive downstream processes, and be
easy to clean post debonding process. In the beginning of wafer bonding, both carrier
wafer and device wafer need to be cleaned and dried to remove particles, contaminants, and moisture, which might induce wafer crack, adhesive bubbling or voiding
and delamination later. Liquid or semi-liquid adhesive is applied by spin coating
approach to cover the wafer surface topography such as C4 bumps. Soft baking is
employed to remove solvents and volatile substances, which might induce adhesive bubbling or voiding later. Inside a vacuum chamber, device wafer and carrier
H. Ma et al.
process, along with post debond cleaning, are investigated. Based on the simple
viscosity definition and wafer geometry, a close-form analytical solution is proposed
for the thermal slide-off wafer debonding process, which can be used for process
control and throughput optimization. The next two processes discussed are laser
scribe and saw dicing, which impact die chipping and delamination. A closed-form
solution of chipping induced by saw dicing is also investigated. In addition, the challenges and solution options for die eject and attach are discussed. Last but not least,
key factors affecting epoxy flow time are studied, and options to reduce the epoxy
keep-out-zone (KOZ) are proposed.
7.2 Brief Overview of TSV Wafer Fabrication Processes
Different TSV wafer fabrication approaches have been reported [6, 7], including Via
First, Via Middle, and Via Last. In Via First, TSV is fabricated before Front-End-ofLine process. In Via Middle, TSV is fabricated after Front-End-of-Line process and
before Back-End-of-Line process. In Via Last, TSV is fabricated after Back-End-ofLine process. Please refer to Chap. 3 for details. The advantages and disadvantages
of different TSV fabrication approaches have been reviewed by several groups and
are beyond the scope of this chapter. In the following, Via Last approach is used
as case study to highlight some key process issues and failure modes. The typical
temporary bonding process flow is shown in Fig. 7.1, and post debond, the typical
singulation process flow is shown in Fig. 7.2.
Post C4 bumping process, device wafer gets edge trimming first to avoid yield loss
due to defects such as wafer edge crack, chipping, and delamination, especially in the
region with adhesive coverage issue [8]. Then, as indicated in Fig. 7.3, device wafer
is attached to carrier wafer by using temporary bonding adhesive [1, 2, 9]. Carrier
wafer can be silicon wafer or optically transparent wafer such as glass, sapphire, and
quartz. Temporary adhesive can be thermal setting polymers, such as epoxies, polyimides, and photoresists, or thermal plastic polymers, such as polydimethylsiloxane
(PDMS), polymethylmethacrylate (PMMA), and polyetherketone (PEEK) [1]. The
material properties of bonding adhesive need to be optimized to improve process
yield and bonding quality [10–13]. The bonding adhesive should have good thermal
resistance and chemical resistance to withstand acid, alkalis, and solvents used at
elevated temperature during different downstream processes, have good adhesion
with both device wafer and carrier wafer to survive downstream processes, and be
easy to clean post debonding process. In the beginning of wafer bonding, both carrier
wafer and device wafer need to be cleaned and dried to remove particles, contaminants, and moisture, which might induce wafer crack, adhesive bubbling or voiding
and delamination later. Liquid or semi-liquid adhesive is applied by spin coating
approach to cover the wafer surface topography such as C4 bumps. Soft baking is
employed to remove solvents and volatile substances, which might induce adhesive bubbling or voiding later. Inside a vacuum chamber, device wafer and carrier