Chapter 7
Fundamentals and Failures in Die
Preparation for 3D Packaging
Huan Ma, Hualiang Shi, and Erasenthiran Poonjolai
7.1 Introduction
Over the past several decades, semiconductor industry has been following Moore’s
law to improve chip performance. Currently, major semiconductor companies such as
Taiwan Semiconductor Manufacturing Company (TSMC) and Intel Corporation are
developing the 7 nm technology node for mass production. However, with reaching
the physical limit, the further scaling of Silicon Front-End-of-Line (FEOL) becomes
more and more challenging. Alternatively, some novel packaging approaches such as
Package-on-Package (POP) and 3D packaging with Through-Silicon-Via (TSV) have
been proposed to further reduce the package form factor, decrease power consumption and improve interconnect speed. This has generated extensive research interests
in the field of new material, process, and equipment.
This chapter is focused on the fundamentals and failures in die preparation for
3D package with TSV. Because several review articles have already summarized
the TSV wafer fabrication processes [1–5], including temporary adhesive wafer
bonding, high aspect ratio silicon etch, wafer singulation, etc., this chapter starts
with a brief overview of general TSV wafer fabrication and singulation processes.
Then, several key process issues, which have not been discussed in previous review
articles, are investigated. First, the temporary wafer bonding process fundamentals,
and the mechanisms and potential solutions of device wafer buckling or wrinkling,
as well as die-level rippling post wafer bonding and thinning are discussed in detail.
Second, the fundamentals and challenges of three main types of wafer debonding
H. Ma
Intel Corporation, 2501 NE Century Blvd, Hillsboro, OR 97124, USA
H. Shi (B) · E. Poonjolai
Intel Corporation, 5000 W. Chandler Blvd, Chandler, AZ 85226, USA
e-mail: shi@gmail.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_7
157
Fundamentals and Failures in Die
Preparation for 3D Packaging
Huan Ma, Hualiang Shi, and Erasenthiran Poonjolai
7.1 Introduction
Over the past several decades, semiconductor industry has been following Moore’s
law to improve chip performance. Currently, major semiconductor companies such as
Taiwan Semiconductor Manufacturing Company (TSMC) and Intel Corporation are
developing the 7 nm technology node for mass production. However, with reaching
the physical limit, the further scaling of Silicon Front-End-of-Line (FEOL) becomes
more and more challenging. Alternatively, some novel packaging approaches such as
Package-on-Package (POP) and 3D packaging with Through-Silicon-Via (TSV) have
been proposed to further reduce the package form factor, decrease power consumption and improve interconnect speed. This has generated extensive research interests
in the field of new material, process, and equipment.
This chapter is focused on the fundamentals and failures in die preparation for
3D package with TSV. Because several review articles have already summarized
the TSV wafer fabrication processes [1–5], including temporary adhesive wafer
bonding, high aspect ratio silicon etch, wafer singulation, etc., this chapter starts
with a brief overview of general TSV wafer fabrication and singulation processes.
Then, several key process issues, which have not been discussed in previous review
articles, are investigated. First, the temporary wafer bonding process fundamentals,
and the mechanisms and potential solutions of device wafer buckling or wrinkling,
as well as die-level rippling post wafer bonding and thinning are discussed in detail.
Second, the fundamentals and challenges of three main types of wafer debonding
H. Ma
Intel Corporation, 2501 NE Century Blvd, Hillsboro, OR 97124, USA
H. Shi (B) · E. Poonjolai
Intel Corporation, 5000 W. Chandler Blvd, Chandler, AZ 85226, USA
e-mail: shi@gmail.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_7
157