4 Microstructure and Mechanical Reliability Issues of TSV
95
Fig. 4.26 Scanning white light interferometry (SWLI) images of the end of a TSV before and after
EM experiments, showing protrusion in the direction of electron flow. A current was passed through
Cu thin films deposited on the top and bottom of the chip through several TSVs simultaneously, for
62 h at 170 °C. The current density through each TSV was 5 × 10 5 A/cm 2 [54]
flow and intrusion at the opposite end), and unlike under thermal cycling conditions,
it accrues continuously [52–54], it may pose a potentially serious reliability challenge, particularly as the current density through the vias increases with decreasing
TSV diameter. It is noted that while this via-migration under EM conditions is noted
in experiments conducted on samples with through-vias with no RDL layer, the
presence of an RDL or BEOL dielectric can constrain such migration and therefore
mitigate it. However, because of the low elastic modulus of the RDL/BEOL dielectric, the effect of any imposed constraint may be limited, and therefore, the effect of
this phenomenon on the stability of the RDL or BEOL layer needs further study.
Recent studies of several TSVs in a Si interposer with metal layers on top of a
TSV have shown two dominant damage mechanisms due to electromigration (EM)
[65]. Generally, protrusion/intrusion of the TSV was suppressed due to the presence
of the back end interconnect structure (BEIS) at the top, and the redistribution layer
(RDL), copper bond-pad and the solder joint at the bottom. However, when subjected
to extreme EM conditions (TSV current density of 1.5 × 10
5 A/cm
2 at 200 °C for
20 days), voids were observed in the metal-1 (M1) layer, where the electron current
crowds following leaving the much larger cross-section TSV, and then leaves after
fanning out again. Such a void is indicated with an arrow in Fig. 4.27a. These types of
EM voids because of current crowding are consistent with routinely noted voids that
form in high density interconnect structures at high current densities. A second type
of damage that was noted under the extreme EM exposure was the concentration
of Sn within the TSV, as shown in the Sn Ka x-ray map (from energy dispersive
spectroscopy) in Fig. 4.27b. It is apparent that Sn has electromigrated in the direction
of electron flow from the Sn-based solder ball, through the metallization below the
TSV, along the TSV-Si interface, and into the TSV. Such alloying of Cu with elements
from the solder under very high current densities can cause significant deterioration
of the electrical properties of the device, as well as mechanical instability due to
volume change due to alloying. As noted above, the experimental conditions in
95
Fig. 4.26 Scanning white light interferometry (SWLI) images of the end of a TSV before and after
EM experiments, showing protrusion in the direction of electron flow. A current was passed through
Cu thin films deposited on the top and bottom of the chip through several TSVs simultaneously, for
62 h at 170 °C. The current density through each TSV was 5 × 10 5 A/cm 2 [54]
flow and intrusion at the opposite end), and unlike under thermal cycling conditions,
it accrues continuously [52–54], it may pose a potentially serious reliability challenge, particularly as the current density through the vias increases with decreasing
TSV diameter. It is noted that while this via-migration under EM conditions is noted
in experiments conducted on samples with through-vias with no RDL layer, the
presence of an RDL or BEOL dielectric can constrain such migration and therefore
mitigate it. However, because of the low elastic modulus of the RDL/BEOL dielectric, the effect of any imposed constraint may be limited, and therefore, the effect of
this phenomenon on the stability of the RDL or BEOL layer needs further study.
Recent studies of several TSVs in a Si interposer with metal layers on top of a
TSV have shown two dominant damage mechanisms due to electromigration (EM)
[65]. Generally, protrusion/intrusion of the TSV was suppressed due to the presence
of the back end interconnect structure (BEIS) at the top, and the redistribution layer
(RDL), copper bond-pad and the solder joint at the bottom. However, when subjected
to extreme EM conditions (TSV current density of 1.5 × 10
5 A/cm
2 at 200 °C for
20 days), voids were observed in the metal-1 (M1) layer, where the electron current
crowds following leaving the much larger cross-section TSV, and then leaves after
fanning out again. Such a void is indicated with an arrow in Fig. 4.27a. These types of
EM voids because of current crowding are consistent with routinely noted voids that
form in high density interconnect structures at high current densities. A second type
of damage that was noted under the extreme EM exposure was the concentration
of Sn within the TSV, as shown in the Sn Ka x-ray map (from energy dispersive
spectroscopy) in Fig. 4.27b. It is apparent that Sn has electromigrated in the direction
of electron flow from the Sn-based solder ball, through the metallization below the
TSV, along the TSV-Si interface, and into the TSV. Such alloying of Cu with elements
from the solder under very high current densities can cause significant deterioration
of the electrical properties of the device, as well as mechanical instability due to
volume change due to alloying. As noted above, the experimental conditions in