Spin Transfer Torque Magnetoresistive Random Access Memory
47
Fig. 2 Illustration of a
rudimentary pMTJ stack
toggle between parallel and antiparallel configurations with respect to the hard layer.
The hard layer serves as a reference for the soft layer in providing a signal readout,
while the soft layer stores the binary information (“0” or “1”) with respect to its
magnetization direction (arrows “up” or “down”). The magnetization direction of
the soft layer should remain unperturbed, until sufficiently large electric current or
magnetic field is sent across the pMTJ to reverse its orientation, which is known as
a write operation. For a read operation, the orientation of the free layer indicates the
resistance state when a small sensing current is passed through the contact electrodes.
Since ferromagnetism is used to represent the binary bit, MRAM is classified
as a non-volatile memory as its storage data does not get erased in the event of a
power cutoff. An array of MTJs can be embedded within the CMOS back-end-ofline (BEOL) interconnects for specific applications, or used as a standalone memory
system.
Emerging memory technologies have to demonstrate compelling advantages to
drive the market towards its development and commercialization. Although often
envisioned to be the “universal memory” that can potentially replace existing memory
technologies [1, 4, 5, 6], MRAM is still considered to be in its infancy stage as it
attempts to compete with cheaper and ultra-dense memory systems such as DRAM
and NAND Flash. The establishment and maturity of CMOS technology raises the
entry level requirement for emerging memory technologies, which will have to
demonstrate the ease of its integration into the existing CMOS BEOL processes.
A list of device performance for different technologies has been summarized in
Table 1. More recently, the roadmaps of several key industry players have outlined
the move towards MRAM as a last level cache [6, 7, 8, 9]. Thus, the current state-ofthe-art design will have to continue undergoing iterations to improve or circumvent
the problems associated with device performance and integration process.
47
Fig. 2 Illustration of a
rudimentary pMTJ stack
toggle between parallel and antiparallel configurations with respect to the hard layer.
The hard layer serves as a reference for the soft layer in providing a signal readout,
while the soft layer stores the binary information (“0” or “1”) with respect to its
magnetization direction (arrows “up” or “down”). The magnetization direction of
the soft layer should remain unperturbed, until sufficiently large electric current or
magnetic field is sent across the pMTJ to reverse its orientation, which is known as
a write operation. For a read operation, the orientation of the free layer indicates the
resistance state when a small sensing current is passed through the contact electrodes.
Since ferromagnetism is used to represent the binary bit, MRAM is classified
as a non-volatile memory as its storage data does not get erased in the event of a
power cutoff. An array of MTJs can be embedded within the CMOS back-end-ofline (BEOL) interconnects for specific applications, or used as a standalone memory
system.
Emerging memory technologies have to demonstrate compelling advantages to
drive the market towards its development and commercialization. Although often
envisioned to be the “universal memory” that can potentially replace existing memory
technologies [1, 4, 5, 6], MRAM is still considered to be in its infancy stage as it
attempts to compete with cheaper and ultra-dense memory systems such as DRAM
and NAND Flash. The establishment and maturity of CMOS technology raises the
entry level requirement for emerging memory technologies, which will have to
demonstrate the ease of its integration into the existing CMOS BEOL processes.
A list of device performance for different technologies has been summarized in
Table 1. More recently, the roadmaps of several key industry players have outlined
the move towards MRAM as a last level cache [6, 7, 8, 9]. Thus, the current state-ofthe-art design will have to continue undergoing iterations to improve or circumvent
the problems associated with device performance and integration process.