Spin Transfer Torque Magnetoresistive
Random Access Memory
Wai Cheung Law and Shawn De Wei Wong
Abstract Faced with an ever-increasing consumer demand for electronics and
the need to remain cost-competitive, a variety of emerging non-volatile memory
(NVM) technologies have been proposed to cater to the performance gaps within the
memory hierarchy system. The magnetoresistive random access memory (MRAM),
an emerging and promising NVM technology, will be the key focus of this chapter.
At the core of MRAM is the magnetic tunnel junction (MTJ), a storage element
embedded within the CMOS process, which has undergone several iterations since
its conception. The novelty of the MTJ structure and the use of magnetic materials
meant that the conventional semiconductor industry have to innovate solutions that
can allow integration with CMOS technology to enable manufacturability. In this
chapter, we will cover the development history of MTJ, the material stack designing
and patterning process.
1 Introduction
Electronics has been an integral part of our daily lives since the age of technology,
and will continue to ever increasingly place an important role especially with the
advent of Artificial Intelligence, 5G and the Internet of Things. One key aspect of
electronics is the memory system, which has been divided into sub-classes to satisfy
the different demands, as shown in Fig. 1. The advantages and limitations of each
class lead to the categorization based on its function to serve and their corresponding
requirements, i.e. fast read/write speed or bit density. The CPU registers sits at the
top of a typical computer memory system hierarchy, occupying between 512 Bytes
to a few kilo Bytes (kB), which is mainly achieved through high speed static random
access memory (SRAM). L0 to L4 caches would be supporting CPU registers in the
form of a mixture of SRAM and dynamic random access memory (DRAM) systems.
Random access memories (RAM) stored in the motherboard falls into the third level
of the hierarchy system, which has a read/write requirement of 10–100 ns. The bulk
W. C. Law (B) · S. De W. Wong
Nanyang Technological University, Singapore, Singapore
e-mail: wlaw002@e.ntu.edu.sg
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
W. S. Lew et al. (eds.), Emerging Non-volatile Memory Technologies,
https://doi.org/10.1007/978-981-15-6912-8_2
45
Random Access Memory
Wai Cheung Law and Shawn De Wei Wong
Abstract Faced with an ever-increasing consumer demand for electronics and
the need to remain cost-competitive, a variety of emerging non-volatile memory
(NVM) technologies have been proposed to cater to the performance gaps within the
memory hierarchy system. The magnetoresistive random access memory (MRAM),
an emerging and promising NVM technology, will be the key focus of this chapter.
At the core of MRAM is the magnetic tunnel junction (MTJ), a storage element
embedded within the CMOS process, which has undergone several iterations since
its conception. The novelty of the MTJ structure and the use of magnetic materials
meant that the conventional semiconductor industry have to innovate solutions that
can allow integration with CMOS technology to enable manufacturability. In this
chapter, we will cover the development history of MTJ, the material stack designing
and patterning process.
1 Introduction
Electronics has been an integral part of our daily lives since the age of technology,
and will continue to ever increasingly place an important role especially with the
advent of Artificial Intelligence, 5G and the Internet of Things. One key aspect of
electronics is the memory system, which has been divided into sub-classes to satisfy
the different demands, as shown in Fig. 1. The advantages and limitations of each
class lead to the categorization based on its function to serve and their corresponding
requirements, i.e. fast read/write speed or bit density. The CPU registers sits at the
top of a typical computer memory system hierarchy, occupying between 512 Bytes
to a few kilo Bytes (kB), which is mainly achieved through high speed static random
access memory (SRAM). L0 to L4 caches would be supporting CPU registers in the
form of a mixture of SRAM and dynamic random access memory (DRAM) systems.
Random access memories (RAM) stored in the motherboard falls into the third level
of the hierarchy system, which has a read/write requirement of 10–100 ns. The bulk
W. C. Law (B) · S. De W. Wong
Nanyang Technological University, Singapore, Singapore
e-mail: wlaw002@e.ntu.edu.sg
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
W. S. Lew et al. (eds.), Emerging Non-volatile Memory Technologies,
https://doi.org/10.1007/978-981-15-6912-8_2
45