RRAM-Based Neuromorphic Computing Systems
411
26. S. Yu, Y. Wu, Y. Chai, J. Provine, H.-S. P. Wong, Characterization of switching parameters and multilevel capability in HfO x/AlO x bi-layer RRAM devices, in Proceedings of
2011 International Symposium on VLSI Technology, Systems and Applications, pp. 1–2: IEEE
(2011)
27. Y. Sun et al., A Ti/AlO x/TaO x/Pt analog synapse for memristive neural network. IEEE Electr.
Dev. Lett. 39(9), 1298–1301 (2018)
28. W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, H. Qian, Improving analog switching in HfO x-based
resistive memory with a thermal enhanced layer. IEEE Electr. Dev Lett. 38(8), 1019–1022
(2017)
29. S. R. Lee et al., Multi-level switching of triple-layered TaOx RRAM with excellent reliability
for storage class memory, in 2012 Symposium on VLSI Technology (VLSIT), pp. 71–72: IEEE
(2012)
30. S. Kim, C. Du, P. Sheridan, W. Ma, S. Choi, W.D. Lu, Experimental demonstration of a
second-order memristor and its ability to biorealistically implement synaptic plasticity. Nano
Lett. 15(3), 2203–2211 (2015)
31. J. Woo, A. Padovani, K. Moon, M. Kwak, L. Larcher, H. Hwang, Linking conductive filament properties and evolution to synaptic behavior of RRAM devices for neuromorphic
applications. IEEE Electron Dev. Lett. 38(9), 1220–1223 (2017)
32. K. Seo et al., Analog memory and spike-timing-dependent plasticity characteristics of
a nanoscale titanium oxide bilayer resistive switching device, Nanotechnology 22(25),
p. 254023, 2011/05/16 (2011)
33. B. Govoreanu et al., Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM):
an area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window
resistive switching cell, in 2013 IEEE International Electron Devices Meeting, pp. 10.2.1–
10.2.4 (2013)
34. B. Govoreanu et al., Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and
excellent variability, in 2016 IEEE Symposium on VLSI Technology, pp. 1–2 (2016)
35. B. Govoreanu et al., A-VMCO: A novel forming-free, self-rectifying, analog memory cell with
low-current operation, nonfilamentary switching and excellent variability, in 2015 Symposium
on VLSI Technology (VLSI Technology), pp. T132–T133 (2015)
36. Z. Chai et al., Impact of RTN on pattern recognition accuracy of RRAM-based synaptic neural
network. IEEE Electr. Dev. Lett. 39(11), 1652–1655 (2018)
37. S. Stathopoulos et al., Multibit memory operation of metal-oxide bi-layer memristors, Sci.
Rep. 7(1), 17532, 2017/12/13 (2017)
38. J. Park, M. Kwak, K. Moon, J. Woo, D. Lee, H. Hwang, TiO x -Based RRAM synapse With 64levels of conductance and symmetric conductance change by adopting a hybrid pulse scheme
for neuromorphic computing. IEEE Electr. Dev. Lett. 37(12), 1559–1562 (2016)
39. C. Hsu et al., Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012
cycles for 3D high-density storage-class memory, in 2013 Symposium on VLSI Technology,
pp. T166–T167 (2013)
40. C.-W. Hsu et al., Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultrahigh endurance three-dimensional storage-class memory, Nanotechnology 25(16), 165202,
2014/03/25 (2014)
41. Y.-F. Wang, Y.-C. Lin, I. T. Wang, T.-P. Lin, and T.-H. Hou, “Characterization and Modeling
of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device,” Scientific Reports, Article vol.
5, p. 10150, 05/08/online 2015
42. I.T. Wang, C.-C. Chang, L.-W. Chiu, T. Chou, T.-H. Hou, 3D Ta/TaOx/TiO 2 /Ti synaptic
array and linearity tuning of weight update for hardware neural network applications.
Nanotechnology 27(36), 365204, 2016/08/02 (2016)
43. I. Wang, Y. Lin, Y. Wang, C. Hsu, and T. Hou, “3D synaptic architecture with ultralow sub-10
fJ energy per spike for neuromorphic computation,” in 2014 IEEE International Electron
Devices Meeting, 2014, pp. 28.5.1–28.5.4
411
26. S. Yu, Y. Wu, Y. Chai, J. Provine, H.-S. P. Wong, Characterization of switching parameters and multilevel capability in HfO x/AlO x bi-layer RRAM devices, in Proceedings of
2011 International Symposium on VLSI Technology, Systems and Applications, pp. 1–2: IEEE
(2011)
27. Y. Sun et al., A Ti/AlO x/TaO x/Pt analog synapse for memristive neural network. IEEE Electr.
Dev. Lett. 39(9), 1298–1301 (2018)
28. W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, H. Qian, Improving analog switching in HfO x-based
resistive memory with a thermal enhanced layer. IEEE Electr. Dev Lett. 38(8), 1019–1022
(2017)
29. S. R. Lee et al., Multi-level switching of triple-layered TaOx RRAM with excellent reliability
for storage class memory, in 2012 Symposium on VLSI Technology (VLSIT), pp. 71–72: IEEE
(2012)
30. S. Kim, C. Du, P. Sheridan, W. Ma, S. Choi, W.D. Lu, Experimental demonstration of a
second-order memristor and its ability to biorealistically implement synaptic plasticity. Nano
Lett. 15(3), 2203–2211 (2015)
31. J. Woo, A. Padovani, K. Moon, M. Kwak, L. Larcher, H. Hwang, Linking conductive filament properties and evolution to synaptic behavior of RRAM devices for neuromorphic
applications. IEEE Electron Dev. Lett. 38(9), 1220–1223 (2017)
32. K. Seo et al., Analog memory and spike-timing-dependent plasticity characteristics of
a nanoscale titanium oxide bilayer resistive switching device, Nanotechnology 22(25),
p. 254023, 2011/05/16 (2011)
33. B. Govoreanu et al., Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM):
an area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window
resistive switching cell, in 2013 IEEE International Electron Devices Meeting, pp. 10.2.1–
10.2.4 (2013)
34. B. Govoreanu et al., Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and
excellent variability, in 2016 IEEE Symposium on VLSI Technology, pp. 1–2 (2016)
35. B. Govoreanu et al., A-VMCO: A novel forming-free, self-rectifying, analog memory cell with
low-current operation, nonfilamentary switching and excellent variability, in 2015 Symposium
on VLSI Technology (VLSI Technology), pp. T132–T133 (2015)
36. Z. Chai et al., Impact of RTN on pattern recognition accuracy of RRAM-based synaptic neural
network. IEEE Electr. Dev. Lett. 39(11), 1652–1655 (2018)
37. S. Stathopoulos et al., Multibit memory operation of metal-oxide bi-layer memristors, Sci.
Rep. 7(1), 17532, 2017/12/13 (2017)
38. J. Park, M. Kwak, K. Moon, J. Woo, D. Lee, H. Hwang, TiO x -Based RRAM synapse With 64levels of conductance and symmetric conductance change by adopting a hybrid pulse scheme
for neuromorphic computing. IEEE Electr. Dev. Lett. 37(12), 1559–1562 (2016)
39. C. Hsu et al., Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012
cycles for 3D high-density storage-class memory, in 2013 Symposium on VLSI Technology,
pp. T166–T167 (2013)
40. C.-W. Hsu et al., Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultrahigh endurance three-dimensional storage-class memory, Nanotechnology 25(16), 165202,
2014/03/25 (2014)
41. Y.-F. Wang, Y.-C. Lin, I. T. Wang, T.-P. Lin, and T.-H. Hou, “Characterization and Modeling
of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device,” Scientific Reports, Article vol.
5, p. 10150, 05/08/online 2015
42. I.T. Wang, C.-C. Chang, L.-W. Chiu, T. Chou, T.-H. Hou, 3D Ta/TaOx/TiO 2 /Ti synaptic
array and linearity tuning of weight update for hardware neural network applications.
Nanotechnology 27(36), 365204, 2016/08/02 (2016)
43. I. Wang, Y. Lin, Y. Wang, C. Hsu, and T. Hou, “3D synaptic architecture with ultralow sub-10
fJ energy per spike for neuromorphic computation,” in 2014 IEEE International Electron
Devices Meeting, 2014, pp. 28.5.1–28.5.4