RRAM-Based Neuromorphic Computing Systems
409
the analog synapse systems, which in general consists of different type of anionbased devices. Several approaches have been implemented to mitigate the conventional anion device limitations, i.e., conductive filament constriction engineering, an
additional thermal enhanced layer, and rigorous programming pulse tuning. On the
other hand, the stochastic nature of the cation-based devices has also been utilized
under stochastic STDP learning rules, which enable a platform with equivalent
functionalities of analog synapse systems.
Various neuromorphic algorithms on RRAM based devices have been comprehensively studied. While research is on-going to develop SNN to facilitate on-chip
learning, the current reliable approach for a real-world application is to do on-chip
inference based on a converted DNN that is pre-trained off-chip. During the mapping
of a DNN to neuromorphic hardware, the hardware constraints, e.g., number of
neurons and synapses, core size, fan in-fan out degrees, routing, and spike traffic
congestion, must be taken into consideration. Should any of the above constraints
are not met, the DNN architecture will have to be modified accordingly to fit into a
specific neuromorphic hardware. Given its small form factor and energy efficiency,
neuromorphic hardware is well suited for edge computing applications such as in the
fields of robotics, surveillance, and unmanned aerial vehicles. It may also be worth
investigating conversion of DNN using different encoding schemes such as temporal
coding or latency coding instead of just rate coding. This would reduce the number
of spikes required to represent an input and result in more efficient computing. In
the long run however, hardware compatible SNN algorithms should be developed
that enable on-chip learning and inference for various applications. This will eliminate the need for conversion of DNN to SNN; the challenge would be how one may
improve the accuracy of such SNN algorithms.
With the aforementioned challenges have been encountered from hardware and
algorithms viewpoint, more research works should adopt the approach that involves
co-design and co-development of hardware, software, and middleware aspects in the
system. This will allow a much more efficient utilization of the devices with certain
advantages and disadvantages for specific target applications.
References
1. C. Koch, Biophysics of computation: information processing in single neurons (computational
neuroscience series). Oxford University Press, Inc. (2004)
2. G.W. Burr et al., Neuromorphic computing using non-volatile memory. Adv Phys 2(1), 89–124
(2017)
3. S.B. Laughlin, T.J. Sejnowski, Communication in neuronal networks. Science 301(5641),
1870 (2003)
4. R. Gopalakrishnan, RRAM based neuromorphic algorithms, arXiv preprint arXiv:1903.02519
(2019)
5. G. Indiveri, E. Linn, S. Ambrogio, ReRAM-based neuromorphic computing. Resistive
Switching, pp. 715–736, 2016/06/22 (2016)
409
the analog synapse systems, which in general consists of different type of anionbased devices. Several approaches have been implemented to mitigate the conventional anion device limitations, i.e., conductive filament constriction engineering, an
additional thermal enhanced layer, and rigorous programming pulse tuning. On the
other hand, the stochastic nature of the cation-based devices has also been utilized
under stochastic STDP learning rules, which enable a platform with equivalent
functionalities of analog synapse systems.
Various neuromorphic algorithms on RRAM based devices have been comprehensively studied. While research is on-going to develop SNN to facilitate on-chip
learning, the current reliable approach for a real-world application is to do on-chip
inference based on a converted DNN that is pre-trained off-chip. During the mapping
of a DNN to neuromorphic hardware, the hardware constraints, e.g., number of
neurons and synapses, core size, fan in-fan out degrees, routing, and spike traffic
congestion, must be taken into consideration. Should any of the above constraints
are not met, the DNN architecture will have to be modified accordingly to fit into a
specific neuromorphic hardware. Given its small form factor and energy efficiency,
neuromorphic hardware is well suited for edge computing applications such as in the
fields of robotics, surveillance, and unmanned aerial vehicles. It may also be worth
investigating conversion of DNN using different encoding schemes such as temporal
coding or latency coding instead of just rate coding. This would reduce the number
of spikes required to represent an input and result in more efficient computing. In
the long run however, hardware compatible SNN algorithms should be developed
that enable on-chip learning and inference for various applications. This will eliminate the need for conversion of DNN to SNN; the challenge would be how one may
improve the accuracy of such SNN algorithms.
With the aforementioned challenges have been encountered from hardware and
algorithms viewpoint, more research works should adopt the approach that involves
co-design and co-development of hardware, software, and middleware aspects in the
system. This will allow a much more efficient utilization of the devices with certain
advantages and disadvantages for specific target applications.
References
1. C. Koch, Biophysics of computation: information processing in single neurons (computational
neuroscience series). Oxford University Press, Inc. (2004)
2. G.W. Burr et al., Neuromorphic computing using non-volatile memory. Adv Phys 2(1), 89–124
(2017)
3. S.B. Laughlin, T.J. Sejnowski, Communication in neuronal networks. Science 301(5641),
1870 (2003)
4. R. Gopalakrishnan, RRAM based neuromorphic algorithms, arXiv preprint arXiv:1903.02519
(2019)
5. G. Indiveri, E. Linn, S. Ambrogio, ReRAM-based neuromorphic computing. Resistive
Switching, pp. 715–736, 2016/06/22 (2016)