402
P. A. Dananjaya et al.
synapses. Half of the RRAM synapses has to be written with low conductance state.
This work is also extended to make the architecture extremely parallel by stretching
the separated weight matrices as in the toeplitz matrix [75]. But, the same disadvantages of poor utilization of axons and synapses as mentioned above will remain.
A slightly different approach of implementation is utilized in IBM’s Truenorth chip
[76]. They have only ternary weights (−1, 0, +1) and uses two crossbar synapses
in a column as a single synapse to implement ternary weights. This will also end up
using double the number of physical synapses on neuromorphic chip compared to
actual number of synapses in a weight kernel. Hence, Truenorth also has a disadvantage of poor utilization of axons and synapses. Truenorth’s actual physical core size,
meaning number of axons × number of neurons, is 256 × 256, but literally their core
size is only 128 × 256 to implement ternary weights.
MAC or weighted-sum operation is considered as one of the most tedious and
yet important processes that involves heavy calculation tasks during the learning
step of a neuromorphic chip. While, the RRAM crossbar array provides a promising
platform to facilitate this process in high density architecture, its implementation on
a large scale NN is still a rather challenging matter. During the MAC operation of
each crossbar column discussed earlier, the problem raised by the inherent sneakpath current issue of the real crossbar array is negligible. However, this issue must
be carefully considered during the programming of the device conductance. The
neighboring cells of the selected RRAM synapse in the array are partially selected
during the operation. In order to mitigate this issue while maintaining the synaptic
device dimension, two-terminal select device is required. The development of the
RRAM synapse alone to meet the requirements of an ideal synaptic device has been
of a great challenge. This leads to an even bigger challenge to develop another select
device that can compatibly work in tandem with the RRAM-based synapse (1S1R).
An alternative of the 1S1R architecture for the real crossbar implementation is
the 1T1R integration. 1T1R synaptic device enables pseudo crossbar array design in
which the RRAM synapse selection in the array is fully controlled by the transistor
gate activation, in the expense of the device dimension. However, 1T1R also has
an advantage over 1S1R synapse in terms of controlling the current flows across
the RRAM synapse. This approach has been largely implemented due to the maturity of the CMOS technology. Several experimental demonstrations of the 1T1Rbased neuromorphic chip have been reported [77, 75]. The first demonstration was
performed by using anion-based TiN/TaO x /HfAl y O x /TiN analog RRAM structure
with 1.2 μm CMOS technology node as cell selector and word line (WL) decoder.
The programming of the synaptic weights into the 1T1R cells were performed with
and without write-verify scheme on 128 × 8 pseudo crossbar array synapses. The
hardware implementation adopted single layer perceptron network to classify the
image data sets into 3 different categories. It consists of 320 input neurons and 3
output neurons with the hyperbolic “tanh” as the activation function. The device
conductance states were mapped to accommodate 256 different weight values (0–
255). The network successfully achieved 91.67 and 87.50% classification accuracy
employing programming with and without write verify scheme. The write-verify
scheme required longer total programming time of 422.4 μs as compared to the
P. A. Dananjaya et al.
synapses. Half of the RRAM synapses has to be written with low conductance state.
This work is also extended to make the architecture extremely parallel by stretching
the separated weight matrices as in the toeplitz matrix [75]. But, the same disadvantages of poor utilization of axons and synapses as mentioned above will remain.
A slightly different approach of implementation is utilized in IBM’s Truenorth chip
[76]. They have only ternary weights (−1, 0, +1) and uses two crossbar synapses
in a column as a single synapse to implement ternary weights. This will also end up
using double the number of physical synapses on neuromorphic chip compared to
actual number of synapses in a weight kernel. Hence, Truenorth also has a disadvantage of poor utilization of axons and synapses. Truenorth’s actual physical core size,
meaning number of axons × number of neurons, is 256 × 256, but literally their core
size is only 128 × 256 to implement ternary weights.
MAC or weighted-sum operation is considered as one of the most tedious and
yet important processes that involves heavy calculation tasks during the learning
step of a neuromorphic chip. While, the RRAM crossbar array provides a promising
platform to facilitate this process in high density architecture, its implementation on
a large scale NN is still a rather challenging matter. During the MAC operation of
each crossbar column discussed earlier, the problem raised by the inherent sneakpath current issue of the real crossbar array is negligible. However, this issue must
be carefully considered during the programming of the device conductance. The
neighboring cells of the selected RRAM synapse in the array are partially selected
during the operation. In order to mitigate this issue while maintaining the synaptic
device dimension, two-terminal select device is required. The development of the
RRAM synapse alone to meet the requirements of an ideal synaptic device has been
of a great challenge. This leads to an even bigger challenge to develop another select
device that can compatibly work in tandem with the RRAM-based synapse (1S1R).
An alternative of the 1S1R architecture for the real crossbar implementation is
the 1T1R integration. 1T1R synaptic device enables pseudo crossbar array design in
which the RRAM synapse selection in the array is fully controlled by the transistor
gate activation, in the expense of the device dimension. However, 1T1R also has
an advantage over 1S1R synapse in terms of controlling the current flows across
the RRAM synapse. This approach has been largely implemented due to the maturity of the CMOS technology. Several experimental demonstrations of the 1T1Rbased neuromorphic chip have been reported [77, 75]. The first demonstration was
performed by using anion-based TiN/TaO x /HfAl y O x /TiN analog RRAM structure
with 1.2 μm CMOS technology node as cell selector and word line (WL) decoder.
The programming of the synaptic weights into the 1T1R cells were performed with
and without write-verify scheme on 128 × 8 pseudo crossbar array synapses. The
hardware implementation adopted single layer perceptron network to classify the
image data sets into 3 different categories. It consists of 320 input neurons and 3
output neurons with the hyperbolic “tanh” as the activation function. The device
conductance states were mapped to accommodate 256 different weight values (0–
255). The network successfully achieved 91.67 and 87.50% classification accuracy
employing programming with and without write verify scheme. The write-verify
scheme required longer total programming time of 422.4 μs as compared to the