RRAM Device Characterizations and Modelling
375
structure, shown in Fig. 29. In detail, under the action of electric field, extra V O
generation results in enlarging the size of CF during SET process. LRS and HRS
gradual decrease firstly, then sharp decrease and stuck in LRS causing the loss of ratio,
which is called as “over SET”. While during RESET process, extra recombination
between O
2− and V O results in an enlarged gap. And finally the resistance of both
LRS and HRS increases and the device cannot be switched to LRS with the primary
SET voltage, which is called as “over RESET” [48].
Cycling endurance degradation is affected by multiple factors. Fantini et al.
demonstrate that it depends on the cell size and layer thickness, shown in Fig. 29c,
and it could be explained that the degradation of endurance after scaling down could
be attributed to the reduced number of ions in the switching layer [65]. Chen et al.
study the impact of RESET amplitude and duration on the endurance degradation,
and it is found that using shorter write pulse, low O-affinity electrode, and high Oaffinity dielectric could obtain significant improvement in endurance performance
[66]. What’s more, the programming condition also has a significant influence on
the endurance degradation [67].
C. Application-Data Retention
Another important performance for evaluating the reliability is data retention, and it
has been reported by several researchers to obtain optimization method of retention
characteristic. Retention refers to the length of time the data can be maintained
in the memory. As a universal metric, the commercial applications of the memory
should ensure that data could be stored for more than 10 years at 85 °C. Based on
the Arrhenius equation, there is an inverse correlation between data retention and
temperature, which the retention time decreases with the temperature increasing. In
order to efficiently evaluate the retention of RRAM cell or RRAM array, baking the
RRAM at high temperature and extrapolating down to the desired temperature is the
common accepted method. Because the failure of retention is a completely stochastic
process, it makes sense to study the retention behavior of a large number of RRAM
device.
Ming Liu et al. demonstrate a temperature-dependent LRS retention failure
behavior of RRAM based on TiO x /Al 2 O 3 bilayer structure. The retention behavior
at 300µA under different temperatures is shown in Fig. 30a. The retention failure
mechanism is attributed to the relationship between the LRS conductivity σ and the
temperature T. Besides, the carriers conduction in CF is similar to the nonmetallic
path formation [66]. More remarkably, σ is related to T with a simple power law
equation, as shown in Fig. 30b. Finally, the resistance deviates from the initial value,
so that the RRAM has a retention failure (Fig. 30c).
Meiran Zhao et al. have investigated the statistical behavior of retention in the
1 Kb filamentary analog RRAM array, and evaluate the impact of retention in the
neural network. The analog switching ability refers to the conductance of the RRAM
varying continuously. The analog data storage could increase the level numbers to
make the analog RRAM a promising emerging device for neuromorphic computing.
In his work, it is found that the conductance distribution of all conductive levels
follows normal distribution with the standard deviation increasing linearly with the
375
structure, shown in Fig. 29. In detail, under the action of electric field, extra V O
generation results in enlarging the size of CF during SET process. LRS and HRS
gradual decrease firstly, then sharp decrease and stuck in LRS causing the loss of ratio,
which is called as “over SET”. While during RESET process, extra recombination
between O
2− and V O results in an enlarged gap. And finally the resistance of both
LRS and HRS increases and the device cannot be switched to LRS with the primary
SET voltage, which is called as “over RESET” [48].
Cycling endurance degradation is affected by multiple factors. Fantini et al.
demonstrate that it depends on the cell size and layer thickness, shown in Fig. 29c,
and it could be explained that the degradation of endurance after scaling down could
be attributed to the reduced number of ions in the switching layer [65]. Chen et al.
study the impact of RESET amplitude and duration on the endurance degradation,
and it is found that using shorter write pulse, low O-affinity electrode, and high Oaffinity dielectric could obtain significant improvement in endurance performance
[66]. What’s more, the programming condition also has a significant influence on
the endurance degradation [67].
C. Application-Data Retention
Another important performance for evaluating the reliability is data retention, and it
has been reported by several researchers to obtain optimization method of retention
characteristic. Retention refers to the length of time the data can be maintained
in the memory. As a universal metric, the commercial applications of the memory
should ensure that data could be stored for more than 10 years at 85 °C. Based on
the Arrhenius equation, there is an inverse correlation between data retention and
temperature, which the retention time decreases with the temperature increasing. In
order to efficiently evaluate the retention of RRAM cell or RRAM array, baking the
RRAM at high temperature and extrapolating down to the desired temperature is the
common accepted method. Because the failure of retention is a completely stochastic
process, it makes sense to study the retention behavior of a large number of RRAM
device.
Ming Liu et al. demonstrate a temperature-dependent LRS retention failure
behavior of RRAM based on TiO x /Al 2 O 3 bilayer structure. The retention behavior
at 300µA under different temperatures is shown in Fig. 30a. The retention failure
mechanism is attributed to the relationship between the LRS conductivity σ and the
temperature T. Besides, the carriers conduction in CF is similar to the nonmetallic
path formation [66]. More remarkably, σ is related to T with a simple power law
equation, as shown in Fig. 30b. Finally, the resistance deviates from the initial value,
so that the RRAM has a retention failure (Fig. 30c).
Meiran Zhao et al. have investigated the statistical behavior of retention in the
1 Kb filamentary analog RRAM array, and evaluate the impact of retention in the
neural network. The analog switching ability refers to the conductance of the RRAM
varying continuously. The analog data storage could increase the level numbers to
make the analog RRAM a promising emerging device for neuromorphic computing.
In his work, it is found that the conductance distribution of all conductive levels
follows normal distribution with the standard deviation increasing linearly with the