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G. J. Lim et al.
Fig. 1 a In the von Neumann architecture, memory and logic are physically separate. They communicate through a shared communications bus, and as a result, prohibits simultaneous bidirectional
data transfer, resulting in the von Neumann bottleneck. b The biological brain and nervous system
of most animals consist of specialised cells called neurons communicating with each other via electrical impulses. The arrows indicate the flow of electrical impulses along pre-synaptic neurons to the
a post-synaptic neuron. c A neural network built upon certain characteristics of the biological brain,
where neurons (grey circles) are connected to each other through synapses with varying weights
(red and blue lines). The arrow indicates the general flow of information in this example of a neural
network
As computers take on more complex tasks, efforts to mitigate the impact as a
result of the bottleneck include increasing the memory bandwidth in and out from
the processor, multithreading, and improving the overall performance of the memory
and processor by increasing transistor density. Over the years, memory density has
steadily increased at a rate described by Moore’s law. Moore’s law is an observation
of the doubling of transistor count approximately every eighteen months. However,
this is accompanied by a plateauing of processor clock rates. The trend of shrinking
transistor size cannot go on indefinitely, due to the approaching physical limits which
will restrict further progress in scaling, and aggravated by issues such as current
leakage and limitations to material choices for ultra-thin gates and channels [1, 2].
Innovations to sustain Moore’s law include building 3D transistors such as FinFETs,
as well as 3D integrated circuit (IC) stacking to increase device density, making
use of the ‘vertical real estate’ [3]. The continued reliance on CMOS transistors
also means that achieving lower power consumption continues to pose a challenge.
Brute processing power through von Neumann computers will not be able to keep
up with ever increasing complexity inherent in computational problems such as
image recognition, machine vision, and other classification tasks. Consequently, there
is increasing demand for more efficient computing by taking inspiration from the
biological brain.
The human brain is an extremely complex structure that exhibits self-awareness,
expresses consciousness and creativity, and is the only organ attempting to understand
itself. The brain employs massively parallel processing [4, 5], is fault tolerant [6],
adaptive (plastic) and capable of self-learning. It manages and coordinates between
sensory inputs, cognition, and motor control via electrical impulses along specialised
cells called neurons as illustrated in Fig. 1b. While the brain consumes a substantial
portion of the body’s total energy, it is remarkably energy efficient when compared
G. J. Lim et al.
Fig. 1 a In the von Neumann architecture, memory and logic are physically separate. They communicate through a shared communications bus, and as a result, prohibits simultaneous bidirectional
data transfer, resulting in the von Neumann bottleneck. b The biological brain and nervous system
of most animals consist of specialised cells called neurons communicating with each other via electrical impulses. The arrows indicate the flow of electrical impulses along pre-synaptic neurons to the
a post-synaptic neuron. c A neural network built upon certain characteristics of the biological brain,
where neurons (grey circles) are connected to each other through synapses with varying weights
(red and blue lines). The arrow indicates the general flow of information in this example of a neural
network
As computers take on more complex tasks, efforts to mitigate the impact as a
result of the bottleneck include increasing the memory bandwidth in and out from
the processor, multithreading, and improving the overall performance of the memory
and processor by increasing transistor density. Over the years, memory density has
steadily increased at a rate described by Moore’s law. Moore’s law is an observation
of the doubling of transistor count approximately every eighteen months. However,
this is accompanied by a plateauing of processor clock rates. The trend of shrinking
transistor size cannot go on indefinitely, due to the approaching physical limits which
will restrict further progress in scaling, and aggravated by issues such as current
leakage and limitations to material choices for ultra-thin gates and channels [1, 2].
Innovations to sustain Moore’s law include building 3D transistors such as FinFETs,
as well as 3D integrated circuit (IC) stacking to increase device density, making
use of the ‘vertical real estate’ [3]. The continued reliance on CMOS transistors
also means that achieving lower power consumption continues to pose a challenge.
Brute processing power through von Neumann computers will not be able to keep
up with ever increasing complexity inherent in computational problems such as
image recognition, machine vision, and other classification tasks. Consequently, there
is increasing demand for more efficient computing by taking inspiration from the
biological brain.
The human brain is an extremely complex structure that exhibits self-awareness,
expresses consciousness and creativity, and is the only organ attempting to understand
itself. The brain employs massively parallel processing [4, 5], is fault tolerant [6],
adaptive (plastic) and capable of self-learning. It manages and coordinates between
sensory inputs, cognition, and motor control via electrical impulses along specialised
cells called neurons as illustrated in Fig. 1b. While the brain consumes a substantial
portion of the body’s total energy, it is remarkably energy efficient when compared