Spintronics for Neuromorphic
Engineering
Gerard Joseph Lim, Calvin Ching Ian Ang, and Wen Siang Lew
Abstract Today’s machine learning and artificial neural networks rely heavily on
conventional electronic circuits. Progress in machine learning models and algorithms
will eventually be limited by issues such as high power dissipation and scaling
challenges posed by CMOS, and it is necessary to resolve these through a bottom-up
approach. Here, we discuss how spintronic devices can overcome energy efficiency
and scalability, and serve as artificial synaptic and neuronal devices using materials
with large spin-orbit coupling, as well as magnetic textures such as chiral domain
walls and skyrmions. We also explore the how these spintronic devices can mimic
the biological brain-inspired neuronal and synaptic behaviours, to develop beyondCMOS neuromorphic hardware for more efficient computation.
1 Introduction
Computers have come a long way since the invention of the first mechanical calculators. Today’s computers use solid state electronic transistors and are designed to
perform complex arithmetic and logical operations with performance that far exceeds
human capability. However, the human brain still outperforms digital computers
when it comes to classification tasks such as recognizing complex patterns, while
utilizing only a fraction of energy that computers require for performing similar tasks.
This is largely due to a completely different architecture between the human brain
and conventional computers. Modern computers are typically built around the von
Neumann architecture that has its advantages in flexibility, simplicity, and economy.
A key limiting factor of this architecture, however, is that a shared communications
bus prevents instruction fetch and data operations from being executed simultaneously, as depicted in Fig. 1a. Therefore, the processor tends to idle while memory
is being accessed, resulting in a limitation known as the von Neumann bottleneck,
which is detrimental to performance and efficiency.
G. J. Lim · C. C. I. Ang · W. S. Lew (B)
Nanyang Technological University, Singapore, Singapore
e-mail: WenSiang@ntu.edu.sg
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
W. S. Lew et al. (eds.), Emerging Non-volatile Memory Technologies,
https://doi.org/10.1007/978-981-15-6912-8_9
297
Engineering
Gerard Joseph Lim, Calvin Ching Ian Ang, and Wen Siang Lew
Abstract Today’s machine learning and artificial neural networks rely heavily on
conventional electronic circuits. Progress in machine learning models and algorithms
will eventually be limited by issues such as high power dissipation and scaling
challenges posed by CMOS, and it is necessary to resolve these through a bottom-up
approach. Here, we discuss how spintronic devices can overcome energy efficiency
and scalability, and serve as artificial synaptic and neuronal devices using materials
with large spin-orbit coupling, as well as magnetic textures such as chiral domain
walls and skyrmions. We also explore the how these spintronic devices can mimic
the biological brain-inspired neuronal and synaptic behaviours, to develop beyondCMOS neuromorphic hardware for more efficient computation.
1 Introduction
Computers have come a long way since the invention of the first mechanical calculators. Today’s computers use solid state electronic transistors and are designed to
perform complex arithmetic and logical operations with performance that far exceeds
human capability. However, the human brain still outperforms digital computers
when it comes to classification tasks such as recognizing complex patterns, while
utilizing only a fraction of energy that computers require for performing similar tasks.
This is largely due to a completely different architecture between the human brain
and conventional computers. Modern computers are typically built around the von
Neumann architecture that has its advantages in flexibility, simplicity, and economy.
A key limiting factor of this architecture, however, is that a shared communications
bus prevents instruction fetch and data operations from being executed simultaneously, as depicted in Fig. 1a. Therefore, the processor tends to idle while memory
is being accessed, resulting in a limitation known as the von Neumann bottleneck,
which is detrimental to performance and efficiency.
G. J. Lim · C. C. I. Ang · W. S. Lew (B)
Nanyang Technological University, Singapore, Singapore
e-mail: WenSiang@ntu.edu.sg
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
W. S. Lew et al. (eds.), Emerging Non-volatile Memory Technologies,
https://doi.org/10.1007/978-981-15-6912-8_9
297