Circuit Design for Non-volatile Magnetic Memory
223
are relatively biased close to ideal “1” and “0” levels, which generates unbalanced
sensing margins.
7 Summary
This chapter presents a brief overview of circuits design for magnetic memory. First,
popular magnetic memory array architectures are explained. Two popular architectures are the 1T1R and crossbar architectures. While the crossbar architecture
provides higher density, the 1T1R architecture is more prevalent in the magnetic
memory. The relatively small TMR ratios of magnetic memory prohibit the proliferation of the crossbar architecture in magnetic memory. Magnetic memory has been
considered as a promising next generation memory solution. However, compared to
CMOS memories such as SRAMs and DRAMs, magnetic memories still need to overcome various challenges in circuits design. This chapter also briefly summarizes the
general challenges in magnetic memory circuits design. After this, various state-ofthe-art write techniques techniques are introduced. They include write driver design
using a current source, bootstrapped word line voltage, field-assisted STT MRAM,
and several probabilistic design techniques. In the probabilistic design techniques,
this chapter explains the write-verify-rewrite with adaptive period (WRAP), verifyone-while-writing (VOW), and variable energy write (VEW) schemes. This chapter
also discusses several sensing techniques such as midpoint reference generation,
self-reference sensing, nondestructive self-reference scheme, symmetrical sensing
architecture, dual-reference-voltage sensing scheme (DVSS), etc.
References
1. S. Yu, P.-Y. Chen, Emerging memory technologies. IEEE Solid-State Circuits Mag. 8(2), 43–56
(2016)
2. X. Fong, Y. Kim, S.H. Choday, K. Roy, Failure mitigation techniques for 1T-1MTJ spin-transfer
torque MRAM Bit-cells. IEEE Trans. VLSI Syst. 22(2), 384–395 (2012) (Write techs. study)
3. T.W. Andre, J.J. Nahas, C.K. Subramanian, B.J. Garni, H.S. Lin, A. Omair, W.L. Martino, A
4-Mb 0.18-µm 1T1MTJ Toggle MRAM with balanced three input sensing scheme and locally
mirrored unidirectional write drivers. IEEE J. Solid-State Circuits 40(1), 301–309, (2005)
(3-input sensing and unidirectional write drivers)
4. D. Gogl, C. Arndt, J.C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers,
M. Lamorey, Y. Lu, T. Maffitt, K. Maloney, W. Obermaier, A. Sturm, H. Viehmann, D. Willmott,
M. Wood, W.J. Gallagher, G. Mueller, A.R. Sitaram, A 16-Mb MRAM featuring bootstrapped.
IEEE J. Solid-State Circuits 40(4), 902–908 (2005) (Boostrapped write driver)
5. X. Bi, Z. Sun, H. Li, W. Wu, Probabilistic design methodology to improve run-time stability and
performance of STT-RAM caches, in Proceedings of IEEE/ACM ICCAD, pp. 88–94 (2012)
(VOW)
6. J. Park, T. Zheng, M. Erez, M. Orshansky, Variation-tolerant write completion circuit for
variable-energy write STT-RAM architecture. IEEE Trans. VLSI Syst. 24(4), 1351–1360
(2016) (write completion, VEW)
223
are relatively biased close to ideal “1” and “0” levels, which generates unbalanced
sensing margins.
7 Summary
This chapter presents a brief overview of circuits design for magnetic memory. First,
popular magnetic memory array architectures are explained. Two popular architectures are the 1T1R and crossbar architectures. While the crossbar architecture
provides higher density, the 1T1R architecture is more prevalent in the magnetic
memory. The relatively small TMR ratios of magnetic memory prohibit the proliferation of the crossbar architecture in magnetic memory. Magnetic memory has been
considered as a promising next generation memory solution. However, compared to
CMOS memories such as SRAMs and DRAMs, magnetic memories still need to overcome various challenges in circuits design. This chapter also briefly summarizes the
general challenges in magnetic memory circuits design. After this, various state-ofthe-art write techniques techniques are introduced. They include write driver design
using a current source, bootstrapped word line voltage, field-assisted STT MRAM,
and several probabilistic design techniques. In the probabilistic design techniques,
this chapter explains the write-verify-rewrite with adaptive period (WRAP), verifyone-while-writing (VOW), and variable energy write (VEW) schemes. This chapter
also discusses several sensing techniques such as midpoint reference generation,
self-reference sensing, nondestructive self-reference scheme, symmetrical sensing
architecture, dual-reference-voltage sensing scheme (DVSS), etc.
References
1. S. Yu, P.-Y. Chen, Emerging memory technologies. IEEE Solid-State Circuits Mag. 8(2), 43–56
(2016)
2. X. Fong, Y. Kim, S.H. Choday, K. Roy, Failure mitigation techniques for 1T-1MTJ spin-transfer
torque MRAM Bit-cells. IEEE Trans. VLSI Syst. 22(2), 384–395 (2012) (Write techs. study)
3. T.W. Andre, J.J. Nahas, C.K. Subramanian, B.J. Garni, H.S. Lin, A. Omair, W.L. Martino, A
4-Mb 0.18-µm 1T1MTJ Toggle MRAM with balanced three input sensing scheme and locally
mirrored unidirectional write drivers. IEEE J. Solid-State Circuits 40(1), 301–309, (2005)
(3-input sensing and unidirectional write drivers)
4. D. Gogl, C. Arndt, J.C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers,
M. Lamorey, Y. Lu, T. Maffitt, K. Maloney, W. Obermaier, A. Sturm, H. Viehmann, D. Willmott,
M. Wood, W.J. Gallagher, G. Mueller, A.R. Sitaram, A 16-Mb MRAM featuring bootstrapped.
IEEE J. Solid-State Circuits 40(4), 902–908 (2005) (Boostrapped write driver)
5. X. Bi, Z. Sun, H. Li, W. Wu, Probabilistic design methodology to improve run-time stability and
performance of STT-RAM caches, in Proceedings of IEEE/ACM ICCAD, pp. 88–94 (2012)
(VOW)
6. J. Park, T. Zheng, M. Erez, M. Orshansky, Variation-tolerant write completion circuit for
variable-energy write STT-RAM architecture. IEEE Trans. VLSI Syst. 24(4), 1351–1360
(2016) (write completion, VEW)