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Contents
3. Process-Induced Stress Engineering in CMOS Technology ............... 53
3.1 Stress Engineering .............................................................................. 55
3.2 Si 1–x Ge x in Source/Drain .................................................................... 57
3.3 Si 1–y C y in Source/Drain ...................................................................... 62
3.4 Shallow Trench Isolation (STI) ..........................................................63
3.5 Contact Etch Stop Layer (CESL) ........................................................64
3.6 Silicidation ............................................................................................ 67
3.7 Stress Memorisation Technique (SMT) ............................................ 68
3.8 Global vs. Local Strain ........................................................................ 69
3.9 BEOL Stress: Through-Silicon Via .................................................... 71
3.10 TSV Modelling ..................................................................................... 78
3.11 Summary ..............................................................................................84
Review Questions ..........................................................................................84
References ....................................................................................................... 85
4. Electronic Properties of Strain-Engineered Semiconductors .............. 87
4.1 Basics of Stress Engineering .............................................................. 89
4.1.1 Stress ........................................................................................ 89
4.2 Stress–Strain Relationships ...............................................................90
4.2.1 Modelling of Stress Generation ........................................... 91
4.3 Strain-Engineered MOSFETs: Current ............................................. 91
4.4 Energy Gap and Band Structure ....................................................... 93
4.4.1 Bulk Si Band Structure .......................................................... 93
4.5 Silicon Conduction Band .................................................................... 94
4.6 Silicon Valence Band ........................................................................... 95
4.7 Band Structure under Stress ............................................................. 96
4.8 Piezoresistive Mobility Model ......................................................... 100
4.9 Strain-Induced Mobility Model ...................................................... 103
4.9.1 Strain-Induced Mobility Model under Electron–
Phonon Interaction .............................................................. 104
4.9.2 Strain-Induced Interaction Potential Scattering by
Acoustic Phonon .................................................................. 104
4.9.3 Transition Probability for Acoustic Phonon Scattering .....106
4.9.4 Strain-Induced Scattering Matrix ...................................... 107
4.9.5 Relaxation Time for Acoustic Phonon Scattering ............ 108
4.10 Implementation of Mobility Model ................................................ 110
4.11 Summary ............................................................................................ 111
Review Questions ........................................................................................ 111
References ..................................................................................................... 112
5. Strain-Engineered MOSFETs ................................................................... 115
5.1 Process Integration............................................................................ 118
5.1.1 Power Consumption ............................................................ 118
5.1.2 Leakage Current ................................................................... 119