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Contents
Preface ......................................................................................................................ix
About the Authors .................................................................................................xi
List of Abbreviations .......................................................................................... xiii
List of Symbols ................................................................................................... xvii
1. Introduction .....................................................................................................1
1.1 Technology Scaling ............................................................................... 4
1.2 Substrate-Induced Strain Engineering ............................................... 5
1.3 Process-Induced Stress Engineering .................................................. 5
1.4 Electronic Properties of Strained Semiconductors ...........................7
1.5 Strain-Engineered MOSFETs ...............................................................7
1.6 Noise in Strain-Engineered Devices .................................................. 8
1.7 Technology CAD of Strain-Engineered MOSFETs ...........................8
1.8 Reliability of Strain-Engineered MOSFETs ..................................... 10
1.9 Process Compact Modelling .............................................................. 10
1.10 Process-Aware Design ........................................................................ 11
1.11 Summary .............................................................................................. 12
Additional Reading ....................................................................................... 13
2. Substrate-Induced Strain Engineering in CMOS Technology ........... 15
2.1 Substrate Engineering ........................................................................ 16
2.2 Strained SiGe Film Growth ............................................................... 18
2.3 Strained SiGe:C Film Growth ............................................................ 21
2.4 Strained Si Films on Relaxed Si 1–x Ge x ..............................................22
2.5 Strained Si on SOI ............................................................................... 25
2.6 Strained Ge Film Growth ................................................................... 27
2.7 Strained Ge MOSFETs ........................................................................ 29
2.8 Heterostructure SiGe/SiGe:C Channel MOSFETs ......................... 32
2.8.1 Band Alignment ..................................................................... 33
2.8.2 Mobility Enhancement .......................................................... 35
2.8.3 Double Quantum Well p-MOSFETs .................................... 36
2.9 Strained Si MOSFETs .......................................................................... 40
2.10 Hybrid Orientation Technology ........................................................44
2.10.1 Device Simulation .................................................................. 45
2.11 Summary .............................................................................................. 50
Review Questions .......................................................................................... 51
References ....................................................................................................... 52