256
Strain-Engineered MOSFETs
Based on the successful verifications, PTMs for 130 nm to 32 nm technology generations have been generated. Figure 9.7 illustrates the trend of nominal I on and I off . Figure  9.8 illustrates the trend of nominal CV/I and switch
power (CV aa
2 ).
The overall map of process sensitivities is shown in Figure  9.9 across
technology generations from 250 nm to 32 nm. Due to increasing process
PTM
Intel
IBM
TI
Fujitsu
TSMC
0.021
0.018
0.015
0.009
0.012
0.006
0.000
0.003 32 nm
45 nm
65 nm
90 nm
130 nm
180 nm
250 nm
10
30
50
70
L eff (nm)
90
110
130
E
ta0
FIGURE 9.6
Trend of DIBL coefficient E ta0 scaling from the 250 nm to 32 nm nodes. (After Zhao, W., Predictive
Technology Modelling for Scaled CMOS, PhD thesis, Arizona State University, 2009.)
FIGURE 9.7
PTM nominal predictions of I on and I off from 250 nm to 32 nm nodes. (After Zhao, W., Predictive
Technology Modelling for Scaled CMOS, PhD thesis, Arizona State University, 2009.)