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8
Reliability and Degradation of
Strain-Engineered MOSFETs
Due to metal-oxide-semiconductor field-effect transistor (MOSFET) downscaling, gate electric field increases. With the increase in electric field, an
increase in chip operating temperature takes place, which is a serious reliability concern in silicon-integrated circuits. Moreover, the recent introduction of high-k gate dielectrics, metal gate materials, high-mobility channels,
and new 3D device architectures has created a need for clear understanding of the reliability issues not only to negative bias temperature instability
(NBTI) but also to positive bias temperature instability (PBTI). Transistors for
three different types of logic are specified in the International Technology
Roadmap for Semiconductors (ITRS): high performance (HP), low standby
power (LSTP), and low operating power (LOP). To meet the performance
and leakage current targets, key technology innovations i.e., high-k gate
dielectrics and metal gate electrodes, ultra-thin body fully depleted siliconon-insulator (SOI) MOSFETs, and multiple-gate MOSFETs, have been introduced in current complementary metal-oxide-semiconductor (CMOS)
processing. New generation devices are taking advantage of the properties
of high-k gate dielectrics, carrier mobility enhancement techniques, and
new 3D architectures. In particular, the Ni fully silicided gate electrodes,
techniques for local strain introduction, such as SiGe in source/drain and
contact etch stop layers (CESLs), and the 3D FinFET technology have led
to different types of reliability issues. This chapter will focus on the bias
temperature instability (BTI) phenomenon in relation to technology scaling.
NBTI and hot-carrier injection (HCI) degradation and their impact on strainengineered MOSFETs are discussed.
Negative bias temperature instability (NBTI) was first reported in 1966 [1].
NBTI is one of the most important threats to p-MOSFETs in VLSI circuits.
The electrical stress (V gs < 0) on the transistor generates traps at the Si/SiO 2
interface. These defect sites increase the threshold voltage, reduce channel mobility of the MOSFETs, induce parasitic capacitances, and degrade
the device performances [2]. NBTI is characterised by an increase in the
absolute threshold voltage, and a degradation of the mobility, drain current, and transconductance under the influence of an applied gate voltage
stress at elevated temperature. It is generally attributed to the creation of
interface traps and oxide charge, although it is not clear which mechanism
is dominant. The mechanism is ascribed to breaking of Si-H bonds at the
8
Reliability and Degradation of
Strain-Engineered MOSFETs
Due to metal-oxide-semiconductor field-effect transistor (MOSFET) downscaling, gate electric field increases. With the increase in electric field, an
increase in chip operating temperature takes place, which is a serious reliability concern in silicon-integrated circuits. Moreover, the recent introduction of high-k gate dielectrics, metal gate materials, high-mobility channels,
and new 3D device architectures has created a need for clear understanding of the reliability issues not only to negative bias temperature instability
(NBTI) but also to positive bias temperature instability (PBTI). Transistors for
three different types of logic are specified in the International Technology
Roadmap for Semiconductors (ITRS): high performance (HP), low standby
power (LSTP), and low operating power (LOP). To meet the performance
and leakage current targets, key technology innovations i.e., high-k gate
dielectrics and metal gate electrodes, ultra-thin body fully depleted siliconon-insulator (SOI) MOSFETs, and multiple-gate MOSFETs, have been introduced in current complementary metal-oxide-semiconductor (CMOS)
processing. New generation devices are taking advantage of the properties
of high-k gate dielectrics, carrier mobility enhancement techniques, and
new 3D architectures. In particular, the Ni fully silicided gate electrodes,
techniques for local strain introduction, such as SiGe in source/drain and
contact etch stop layers (CESLs), and the 3D FinFET technology have led
to different types of reliability issues. This chapter will focus on the bias
temperature instability (BTI) phenomenon in relation to technology scaling.
NBTI and hot-carrier injection (HCI) degradation and their impact on strainengineered MOSFETs are discussed.
Negative bias temperature instability (NBTI) was first reported in 1966 [1].
NBTI is one of the most important threats to p-MOSFETs in VLSI circuits.
The electrical stress (V gs < 0) on the transistor generates traps at the Si/SiO 2
interface. These defect sites increase the threshold voltage, reduce channel mobility of the MOSFETs, induce parasitic capacitances, and degrade
the device performances [2]. NBTI is characterised by an increase in the
absolute threshold voltage, and a degradation of the mobility, drain current, and transconductance under the influence of an applied gate voltage
stress at elevated temperature. It is generally attributed to the creation of
interface traps and oxide charge, although it is not clear which mechanism
is dominant. The mechanism is ascribed to breaking of Si-H bonds at the