1
1
Introduction
It is not the strongest of the species that survives, nor the most intelligent, but the one most responsive to changes.
—Charles Darwin
In the field of microelectronics, the planar silicon metal-oxide-semiconductor
field-effect transistor (MOSFET) is perhaps the most important invention. It
started in 1928 when J. E. Lilienfeld proposed the concept of field-effect conductivity modulation and the MOSFET. William Shockley, John Bardeen, and
Walter Brattain invented the transistor in 1947, and with the discovery of silicon dioxide (SiO 2 ) passivation for the Si by Atalla in 1958, the Si MOSFET era
started. Since then MOSFET performance has been improved at a dramatic
rate via gate length scaling, and complementary metal-oxide-semiconductor
(CMOS) is currently the dominant technology for integrated circuits. As the
technology scales almost every 2 years, the transistor integration capacity
doubles (Moore’s law), gate delay reduces by 30%, energy per logic operation
reduces by 65%, and power consumption reduces by 50%. Table 1.1 shows
CMOS technology outlook extrapolated from the current International
Technology Roadmap for Semiconductors (ITRS) trends. However, conventional CMOS scaling has now approached the fundamental limits, which
include leakage in channel and gate, diminished bulk effect, transport in
silicon, and increased power dissipation. The huge costs of scaling CMOS
devices according to Moore’s law have now left the silicon industry at a
crossroad. As technology scales, the cost of a transistor goes down, but the
cost of fabrication facilities, cost of mask set, and turnaround time increase
for each generation. Lithographic challenges for future technology nodes
have become a major concern. Implementation of extreme ultraviolet radiation (EUV) will help continue transistor size scaling. Although it will allow
for increased device density, current scaling issues will be a major concern at
smaller gate length devices. ITRS 2009 has projected scaling of the advanced
MOSFETs covering the next 15 years through 2022. The evolution of the Si
process technology after the 130 nm node is shown in Figure 1.1. Technology
challenges for 10 nm CMOS and beyond will face process limitations such
as patterning ultra-fine and random features, ultra-thin gate dielectric (∼3 Ǻ),
and ultra-shallow junction (∼3 nm). In the following, we shall address the
recent developments, which have been the subject of a major research drive
for the last 10 years aimed at finding new avenues to enhance the performance of MOSFETs.
1
Introduction
It is not the strongest of the species that survives, nor the most intelligent, but the one most responsive to changes.
—Charles Darwin
In the field of microelectronics, the planar silicon metal-oxide-semiconductor
field-effect transistor (MOSFET) is perhaps the most important invention. It
started in 1928 when J. E. Lilienfeld proposed the concept of field-effect conductivity modulation and the MOSFET. William Shockley, John Bardeen, and
Walter Brattain invented the transistor in 1947, and with the discovery of silicon dioxide (SiO 2 ) passivation for the Si by Atalla in 1958, the Si MOSFET era
started. Since then MOSFET performance has been improved at a dramatic
rate via gate length scaling, and complementary metal-oxide-semiconductor
(CMOS) is currently the dominant technology for integrated circuits. As the
technology scales almost every 2 years, the transistor integration capacity
doubles (Moore’s law), gate delay reduces by 30%, energy per logic operation
reduces by 65%, and power consumption reduces by 50%. Table 1.1 shows
CMOS technology outlook extrapolated from the current International
Technology Roadmap for Semiconductors (ITRS) trends. However, conventional CMOS scaling has now approached the fundamental limits, which
include leakage in channel and gate, diminished bulk effect, transport in
silicon, and increased power dissipation. The huge costs of scaling CMOS
devices according to Moore’s law have now left the silicon industry at a
crossroad. As technology scales, the cost of a transistor goes down, but the
cost of fabrication facilities, cost of mask set, and turnaround time increase
for each generation. Lithographic challenges for future technology nodes
have become a major concern. Implementation of extreme ultraviolet radiation (EUV) will help continue transistor size scaling. Although it will allow
for increased device density, current scaling issues will be a major concern at
smaller gate length devices. ITRS 2009 has projected scaling of the advanced
MOSFETs covering the next 15 years through 2022. The evolution of the Si
process technology after the 130 nm node is shown in Figure 1.1. Technology
challenges for 10 nm CMOS and beyond will face process limitations such
as patterning ultra-fine and random features, ultra-thin gate dielectric (∼3 Ǻ),
and ultra-shallow junction (∼3 nm). In the following, we shall address the
recent developments, which have been the subject of a major research drive
for the last 10 years aimed at finding new avenues to enhance the performance of MOSFETs.