207
Technology CAD of Strain-Engineered MOSFETs
Validation is considered to be more difficult than model or code development.
Results are compared after prediction. For example, a measured 2D dopant
profile can be compared with SUPREM predictions, and both can be used as
inputs to a device simulator for predictions to assess comparisons for actual
device results. An improvement in predictability will also provide greater confidence in reliability assessments and in process/structure configurations that
improve robustness.
Since the speed of metal-oxide-semiconductor field-effect transistor
(MOSFET) is intrinsically limited by the carrier transit time, the most obvious
approach to improve the device speed is to reduce the gate length. However,
the 2D effects due to the gate length scaling affect the threshold voltage and
subthreshold slope and increase the off-state current. When the gate length is
aggressively scaled, the gate begins to lose control over the channel and the parasitic conduction layers, resulting in saturation, possibly a reduction of transconductance, and an increase of drain conductance. It is now well recognised
that under the sub-100 nm regime, conventional MOSFET scaling concepts will
be confronted with physical limitations—the lattice constant of Si. The major
problems of scaling down the conventional MOSFETs include (1) quantum
mechanical tunneling through the thin gate oxide, from source to drain and
from drain to body; (2) threshold voltage control induced by random doping
effects; (3) short-channel effects and mobility degradation; and (4) process control of thin layer uniformity and accurate lithography and implantation.
To extend the lifetime of the Si-based complementary metal-oxidesemiconductor (CMOS) technology, devices with new structures or new
materials need to be considered [2]. Several performance boosters have
been proposed in the literature, and the International Technology Roadmap
for Semiconductors suggests that one or more technology boosters may be
required for devices beyond the 45 nm technology node in order to sustain
the increase of intrinsic device speed. Process steps introduce compressive
stress in the Si channel of a MOSFET. Through appropriate strain engineering, such as shallow trench isolation (STI), embedded SiGe under the source/
drain region, and the cap layer or silicidation process (all of which have been
incorporated into Intel’s current 90 nm technology) performance enhancement can be achieved. In comparison with the process-induced strain,
strained Si pseudomorphically grown on a relaxed SiGe layer is a commonly
adopted approach to achieve tensile strain. Strained Si on a relaxed SiGe buffer for CMOS applications has been studied for more than 15 years. Progress
has also been made toward the evolution of the strained Si MOS structure, such as the strained Si on SiGe-on-insulator (SGOI) and the strained
Si-directly-on-insulator (SSDOI). With a highly strained Si channel or using
a different orientation (110) substrate in p-MOSFETs, the performance match
between the n- and p-MOSFETs for CMOS applications might be achieved.
In this chapter we present the results of our simulation study on the evolution of Si-based MOSFETs via the incorporation of new materials, for example, strained Si, to predict the future device performance and the scaling
Technology CAD of Strain-Engineered MOSFETs
Validation is considered to be more difficult than model or code development.
Results are compared after prediction. For example, a measured 2D dopant
profile can be compared with SUPREM predictions, and both can be used as
inputs to a device simulator for predictions to assess comparisons for actual
device results. An improvement in predictability will also provide greater confidence in reliability assessments and in process/structure configurations that
improve robustness.
Since the speed of metal-oxide-semiconductor field-effect transistor
(MOSFET) is intrinsically limited by the carrier transit time, the most obvious
approach to improve the device speed is to reduce the gate length. However,
the 2D effects due to the gate length scaling affect the threshold voltage and
subthreshold slope and increase the off-state current. When the gate length is
aggressively scaled, the gate begins to lose control over the channel and the parasitic conduction layers, resulting in saturation, possibly a reduction of transconductance, and an increase of drain conductance. It is now well recognised
that under the sub-100 nm regime, conventional MOSFET scaling concepts will
be confronted with physical limitations—the lattice constant of Si. The major
problems of scaling down the conventional MOSFETs include (1) quantum
mechanical tunneling through the thin gate oxide, from source to drain and
from drain to body; (2) threshold voltage control induced by random doping
effects; (3) short-channel effects and mobility degradation; and (4) process control of thin layer uniformity and accurate lithography and implantation.
To extend the lifetime of the Si-based complementary metal-oxidesemiconductor (CMOS) technology, devices with new structures or new
materials need to be considered [2]. Several performance boosters have
been proposed in the literature, and the International Technology Roadmap
for Semiconductors suggests that one or more technology boosters may be
required for devices beyond the 45 nm technology node in order to sustain
the increase of intrinsic device speed. Process steps introduce compressive
stress in the Si channel of a MOSFET. Through appropriate strain engineering, such as shallow trench isolation (STI), embedded SiGe under the source/
drain region, and the cap layer or silicidation process (all of which have been
incorporated into Intel’s current 90 nm technology) performance enhancement can be achieved. In comparison with the process-induced strain,
strained Si pseudomorphically grown on a relaxed SiGe layer is a commonly
adopted approach to achieve tensile strain. Strained Si on a relaxed SiGe buffer for CMOS applications has been studied for more than 15 years. Progress
has also been made toward the evolution of the strained Si MOS structure, such as the strained Si on SiGe-on-insulator (SGOI) and the strained
Si-directly-on-insulator (SSDOI). With a highly strained Si channel or using
a different orientation (110) substrate in p-MOSFETs, the performance match
between the n- and p-MOSFETs for CMOS applications might be achieved.
In this chapter we present the results of our simulation study on the evolution of Si-based MOSFETs via the incorporation of new materials, for example, strained Si, to predict the future device performance and the scaling