All Optical Universal Logic TAND Gate Using a Single …
173
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
83
84
85
86
87
88
REO (%)
Control Power (mW)
REO
Fig. 7 Variations of REO with control power
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
0
0.5
1
Time(ps)
Output Power(a.u)
Fig. 8 Output bit pattern at a speed of 2 TBit/s
4 TAND as a Universal Logic
TAND gate can be used to design all basic gates and is universal one. In the following
sections, NOT, AND, and OR gates are designed and explained.
173
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
83
84
85
86
87
88
REO (%)
Control Power (mW)
REO
Fig. 7 Variations of REO with control power
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
0
0.5
1
Time(ps)
Output Power(a.u)
Fig. 8 Output bit pattern at a speed of 2 TBit/s
4 TAND as a Universal Logic
TAND gate can be used to design all basic gates and is universal one. In the following
sections, NOT, AND, and OR gates are designed and explained.