736
24 Transistors
(d)
(e)
Fig. 24.51 Thermal annealing of 100 nm thick film of amorphous silicon (fabricated from LPCVD and amorphized by
100 keV Si + implantation with a dose of 5 × 10 15 cm −2 ). TEM images and diffraction patterns (insets) for amorphized
Si after a 4 h, b 5.25 h and c 7.1 h annealing at T = 630 ◦ C. The crystalline fractions are 2%, 28% and 87%, respectively.
d Crystalline fraction as a function of annealing time for various annealing temperatures as labeled. Symbols are experimental data, solid lines depict theory considering grain nucleation and growth. e Final grain size for various annealing
temperature. Dashed line is exponential with a slope of 0.6 eV. Adapted from [2121]
In Fig. 24.51 the effect of thermal annealing of amorphous silicon is shown. The annealing time
necessary to convert the amorphous phase completely to polycrystalline, e.g. 10 h at 640
◦ C, depends
largely on temperature as detailed in [2121, 2122] (Fig. 24.51a) with a large activation energy of 3.9 eV.
Also the final grain size is temperature dependent (Fig. 24.51b).
The introduction of certain metals like Pd [2123], Al [2124], Au [2125] or Ni [2126] induces
crystallization and allows for much lower annealing temperatures. Pd and Ni create silicides that play
an important role for the grain nucleation or growth front. Au and Al are solved in the bulk but have
a similar effect. For example, using Pd complete crystallization of a 150 nm thick a-Si film deposited
at 480
◦ C can be achieved by thermal annealing after 10 h at only 500
◦ C [2127] (using metal-induced
lateral crystallization, MILC).
24.6.2 TFT Devices
A schematic cross section of an amorphous silicon-based TFT is shown in Fig. 24.52a. Carriers in
amorphous silicon have a low mobility typically less than 1 cm
2 /Vs [2128, 2129]. As-grown polycrys-
24 Transistors
(d)
(e)
Fig. 24.51 Thermal annealing of 100 nm thick film of amorphous silicon (fabricated from LPCVD and amorphized by
100 keV Si + implantation with a dose of 5 × 10 15 cm −2 ). TEM images and diffraction patterns (insets) for amorphized
Si after a 4 h, b 5.25 h and c 7.1 h annealing at T = 630 ◦ C. The crystalline fractions are 2%, 28% and 87%, respectively.
d Crystalline fraction as a function of annealing time for various annealing temperatures as labeled. Symbols are experimental data, solid lines depict theory considering grain nucleation and growth. e Final grain size for various annealing
temperature. Dashed line is exponential with a slope of 0.6 eV. Adapted from [2121]
In Fig. 24.51 the effect of thermal annealing of amorphous silicon is shown. The annealing time
necessary to convert the amorphous phase completely to polycrystalline, e.g. 10 h at 640
◦ C, depends
largely on temperature as detailed in [2121, 2122] (Fig. 24.51a) with a large activation energy of 3.9 eV.
Also the final grain size is temperature dependent (Fig. 24.51b).
The introduction of certain metals like Pd [2123], Al [2124], Au [2125] or Ni [2126] induces
crystallization and allows for much lower annealing temperatures. Pd and Ni create silicides that play
an important role for the grain nucleation or growth front. Au and Al are solved in the bulk but have
a similar effect. For example, using Pd complete crystallization of a 150 nm thick a-Si film deposited
at 480
◦ C can be achieved by thermal annealing after 10 h at only 500
◦ C [2127] (using metal-induced
lateral crystallization, MILC).
24.6.2 TFT Devices
A schematic cross section of an amorphous silicon-based TFT is shown in Fig. 24.52a. Carriers in
amorphous silicon have a low mobility typically less than 1 cm
2 /Vs [2128, 2129]. As-grown polycrys-