24.5 MOSFETs
729
(a)
(b)
Fig. 24.38 Schematic of a a n-type and b p-type tunneling FET (TFET). D is reversely biased, i.e. positive for NTFET
and negative for PTFET. The grey areas represent the gate oxide, the arrows denote the spatial position of tunneling
(surface tunneling juction) for sufficient (NTFET: positive, PTFET: negative) gate voltage
Fig. 24.39 MOSFET with
a floating gate and b MIOS
structure
V G
V D
V BS
n-Si
p+
V G
V D
V BS
n-Si
p+
(a)
(b)
floating
gate
(oxide)
Fig. 24.40 Cross sections
a perpendicular and b
parallel to the control gate
line of a 4 Gb, 73 nm SLC
flash memory (Samsung
K9F4G08U0M). ‘CG’
denotes the control gate,
‘FG’ the floating gate, ‘TO’
the tunneling oxide, ‘ONO’
the oxide/nitride/oxide
insulator stack, and ‘STI’
the shallow trench
insulation. Adapted
from [2074]
(a)
(b)
and off state. The storage time of the charge can be of the order of 100 years. Since tunneling limits the
charge retention, the oxide must be sufficiently thick. In Fig. 24.40 a cross section of a 4 Gb, 73 nm SLC
(single-level cell) flash memory is shown. The lower insulator (tunneling oxide at the channel) consist
of 7.2 nm SiO 2 , the upper insulator (insulator 1 in Fig. 24.39a) is a 18 nm thick oxide/nitride/oxide
(ONO) stack. The floating gate has a 90 × 90 nm
2 footprint, is about 86 nm high and consists of two
polysilicon layers.
In a SLC memory the floating gate has two states, a certain charge value and the erased state. In a
MLC (multi-level cell) the gate can store several charge states which can be sensed as different logic
states, e.g. 2
2
= 4 states. This increases the storage density, lowering cost per bit, but also increases
the complexity. Typical endurance of SLC is at least 10
6 program–erase cycles. SLC cells so far have
about ten times higher endurance (possible number of read–write cycles) and lower power consumption
than MLC. Generally SLC flash memory is considered industrial grade and MLC flash is considered
729
(a)
(b)
Fig. 24.38 Schematic of a a n-type and b p-type tunneling FET (TFET). D is reversely biased, i.e. positive for NTFET
and negative for PTFET. The grey areas represent the gate oxide, the arrows denote the spatial position of tunneling
(surface tunneling juction) for sufficient (NTFET: positive, PTFET: negative) gate voltage
Fig. 24.39 MOSFET with
a floating gate and b MIOS
structure
V G
V D
V BS
n-Si
p+
V G
V D
V BS
n-Si
p+
(a)
(b)
floating
gate
(oxide)
Fig. 24.40 Cross sections
a perpendicular and b
parallel to the control gate
line of a 4 Gb, 73 nm SLC
flash memory (Samsung
K9F4G08U0M). ‘CG’
denotes the control gate,
‘FG’ the floating gate, ‘TO’
the tunneling oxide, ‘ONO’
the oxide/nitride/oxide
insulator stack, and ‘STI’
the shallow trench
insulation. Adapted
from [2074]
(a)
(b)
and off state. The storage time of the charge can be of the order of 100 years. Since tunneling limits the
charge retention, the oxide must be sufficiently thick. In Fig. 24.40 a cross section of a 4 Gb, 73 nm SLC
(single-level cell) flash memory is shown. The lower insulator (tunneling oxide at the channel) consist
of 7.2 nm SiO 2 , the upper insulator (insulator 1 in Fig. 24.39a) is a 18 nm thick oxide/nitride/oxide
(ONO) stack. The floating gate has a 90 × 90 nm
2 footprint, is about 86 nm high and consists of two
polysilicon layers.
In a SLC memory the floating gate has two states, a certain charge value and the erased state. In a
MLC (multi-level cell) the gate can store several charge states which can be sensed as different logic
states, e.g. 2
2
= 4 states. This increases the storage density, lowering cost per bit, but also increases
the complexity. Typical endurance of SLC is at least 10
6 program–erase cycles. SLC cells so far have
about ten times higher endurance (possible number of read–write cycles) and lower power consumption
than MLC. Generally SLC flash memory is considered industrial grade and MLC flash is considered