622
22 Light-to-Electricity Conversion
Fig. 22.48 a Array of
16-pixel (1000 × 405 μm 2 )
silicon APDs (width of
housing: 15 mm). From
[1864]. b 1024-pixel
(25 × 500 μm 2 ) InGaAs
photodiode array (width of
array: 1 inch). From [1865]
(a)
(b)
Fig. 22.49 a Scheme of
four-quadrant
photodetector with sections
‘a’, ‘b’, ‘c’ and ‘d’. b
image of four-quadrant
silicon photodetector with
circuit board (diameter of
active area: 8 mm, gap
between sectors: 0.2 mm).
From [1866].
(a)
b
a
c
d
(b)
(a)
(b)
Fig. 22.50 a Schematic cross-section of global shutter pixel with light pipe for optimized collection. α denotes the taper
angle, PD: photodiode, MN: buried memory node to store the charges until readout. b Cross-section SEM image of such
pixel. Adapted from [1867]
fashion (Fig. 22.50). This so-called ’global shutter’ pixel is connected to a local memory cell that allows
simultaneous intermediate signal storage of all individual pixels in order to enable high framerate (slowmotion) video operation without spatio-temporal distortions due to a sequential read-out sequence. For
such fast signal management, a three-layer scheme has been developed fusing three wafers for the
photodiodes, the dynamic random access memory (DRAM) and the logic layer for the image signal
processing (Fig. 22.51) [1868].
A special CMOS image sensor has built-in grating structures to allow detection of the linear polarization state [1869]. As depicted in Fig. 22.52, each pixel is subdivided in four with gratings in 0
◦ , 90
◦ ,
and ±45
◦ directions between the on-chip lenses and the photodiodes to create sensitivity to the linear
polarization state of the incoming light.
22 Light-to-Electricity Conversion
Fig. 22.48 a Array of
16-pixel (1000 × 405 μm 2 )
silicon APDs (width of
housing: 15 mm). From
[1864]. b 1024-pixel
(25 × 500 μm 2 ) InGaAs
photodiode array (width of
array: 1 inch). From [1865]
(a)
(b)
Fig. 22.49 a Scheme of
four-quadrant
photodetector with sections
‘a’, ‘b’, ‘c’ and ‘d’. b
image of four-quadrant
silicon photodetector with
circuit board (diameter of
active area: 8 mm, gap
between sectors: 0.2 mm).
From [1866].
(a)
b
a
c
d
(b)
(a)
(b)
Fig. 22.50 a Schematic cross-section of global shutter pixel with light pipe for optimized collection. α denotes the taper
angle, PD: photodiode, MN: buried memory node to store the charges until readout. b Cross-section SEM image of such
pixel. Adapted from [1867]
fashion (Fig. 22.50). This so-called ’global shutter’ pixel is connected to a local memory cell that allows
simultaneous intermediate signal storage of all individual pixels in order to enable high framerate (slowmotion) video operation without spatio-temporal distortions due to a sequential read-out sequence. For
such fast signal management, a three-layer scheme has been developed fusing three wafers for the
photodiodes, the dynamic random access memory (DRAM) and the logic layer for the image signal
processing (Fig. 22.51) [1868].
A special CMOS image sensor has built-in grating structures to allow detection of the linear polarization state [1869]. As depicted in Fig. 22.52, each pixel is subdivided in four with gratings in 0
◦ , 90
◦ ,
and ±45
◦ directions between the on-chip lenses and the photodiodes to create sensitivity to the linear
polarization state of the incoming light.